Fix for MUL instruction on the v850

	* sim/v850/simops.c (Multiply64): Properly test if we need to
	negate either of the operands.

	* sim/testsuite/v850/mul.cgs: New test.

diff --git a/sim/testsuite/v850/mul.cgs b/sim/testsuite/v850/mul.cgs
new file mode 100644 (file)
index 0000000..7d19b70
--- /dev/null
+++ b/sim/testsuite/v850/mul.cgs
@@ -0,0 +1,15 @@
+# v850e mul
+# mach: v850e
+# as(v850e): -mv850e
+
+       .include "testutils.inc"
+
+# Trivial regression test for incorrect sign bit handling in mul
+
+       seti    -10, r1
+       seti    2, r2
+       mul     r1, r2, r3
+       reg     r2, -20
+       reg     r3, -1
+
+       pass

diff --git a/sim/v850/simops.c b/sim/v850/simops.c
index 8fac8bd9891124ffd3236fae87e069ca51bf2004..d2640577fc81c20b1ae9ec4e1395d33aa1c03932 100644 (file)
--- a/sim/v850/simops.c
+++ b/sim/v850/simops.c
@@ -339,10 +339,10 @@ Multiply64 (int sign, unsigned long op0)
          
       sign = (op0 ^ op1) & 0x80000000;
          
-      if (((signed long) op0) < 0)
+      if (op0 & 0x80000000)
        op0 = - op0;
          
-      if (((signed long) op1) < 0)
+      if (op1 & 0x80000000)
        op1 = - op1;
     }