RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
{ ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSWSS,
RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
- { ALTIVEC_BUILTIN_VEC_VPKSWSS, ALTIVEC_BUILTIN_VPKSWSS,
- RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
- { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS,
- RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
{ ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
{ ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS,
RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
+ { ALTIVEC_BUILTIN_VEC_VPKSWSS, ALTIVEC_BUILTIN_VPKSWSS,
+ RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
+ { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS,
+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
{ ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VPKSHSS,
RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
{ ALTIVEC_BUILTIN_VEC_VPKUHUS, ALTIVEC_BUILTIN_VPKUHUS,
RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
{ P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
+ { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
+ RS6000_BTI_V16QI, 0, 0, 0 },
+ { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
+ RS6000_BTI_unsigned_V16QI, 0, 0, 0 },
{ P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B,
RS6000_BTI_V16QI, RS6000_BTI_V4SI,
{ P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,
RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
- { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
- RS6000_BTI_V16QI, 0, 0, 0 },
- { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
- RS6000_BTI_unsigned_V16QI, 0, 0, 0 },
-
{ P9V_BUILTIN_VEC_VSLV, P9V_BUILTIN_VSLV,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_unsigned_V16QI, 0 },
return vec_nabs (x);
}
+vector signed int
+test_vsi_packs_vsll_vsll (vector signed long long x,
+ vector signed long long y)
+{
+ return vec_packs (x, y);
+}
+
+vector unsigned int
+test_vui_packs_vull_vull (vector unsigned long long x,
+ vector unsigned long long y)
+{
+ return vec_packs (x, y);
+}
+
/* Expected test results:
test_eq_long_long 1 vcmpequd inst
test_pack_float 1 vpkudum inst
- test_nabs_long_long 1 vspltisw, 1 vsubudm, 1 vminsd */
+ test_nabs_long_long 1 vspltisw, 1 vsubudm, 1 vminsd
+ test_vsi_packs_vsll_vsll 1 vpksdss
+ test_vui_packs_vull_vull 1 vpkudus */
/* { dg-final { scan-assembler-times "vcmpequd" 1 } } */
/* { dg-final { scan-assembler-times "vpkudum" 1 } } */
/* { dg-final { scan-assembler-times "vspltisw" 1 } } */
/* { dg-final { scan-assembler-times "vsubudm" 1 } } */
/* { dg-final { scan-assembler-times "vminsd" 1 } } */
+/* { dg-final { scan-assembler-times "vpksdss" 1 } } */
+/* { dg-final { scan-assembler-times "vpkudus" 1 } } */