boards/arty : Add directly connected spi clk pin to avoid need for STARTUPE2

diff --git a/litex/boards/platforms/arty.py b/litex/boards/platforms/arty.py
index aa38cf0a71eb1c426271b8660efa65274d365307..f03f9884ade0471f87bc9294296ab815e3b2972d 100644 (file)
--- a/litex/boards/platforms/arty.py
+++ b/litex/boards/platforms/arty.py
@@ -79,13 +79,15 @@ _io = [
         IOStandard("LVCMOS33"),
     ),
 
-    ("spiflash4x", 0,  # clock needs to be accessed through STARTUPE2
+    ("spiflash4x", 0,
         Subsignal("cs_n", Pins("L13")),
+        Subsignal("clk", Pins("L16")),
         Subsignal("dq", Pins("K17", "K18", "L14", "M14")),
         IOStandard("LVCMOS33")
     ),
-    ("spiflash", 0,  # clock needs to be accessed through STARTUPE2
+    ("spiflash", 0,
         Subsignal("cs_n", Pins("L13")),
+        Subsignal("clk", Pins("L16")),
         Subsignal("mosi", Pins("K17")),
         Subsignal("miso", Pins("K18")),
         Subsignal("wp", Pins("L14")),