delete handle;
}
+int cxxrtl_eval(cxxrtl_handle handle) {
+ return handle->module->eval();
+}
+
+int cxxrtl_commit(cxxrtl_handle handle) {
+ return handle->module->commit();
+}
+
size_t cxxrtl_step(cxxrtl_handle handle) {
return handle->module->step();
}
// Release all resources used by a design and its handle.
void cxxrtl_destroy(cxxrtl_handle handle);
+// Evaluate the design, propagating changes on inputs to the `next` value of internal state and
+// output wires.
+//
+// Returns 1 if the design is known to immediately converge, 0 otherwise.
+int cxxrtl_eval(cxxrtl_handle handle);
+
+// Commit the design, replacing the `curr` value of internal state and output wires with the `next`
+// value.
+//
+// Return 1 if any of the `curr` values, 0 otherwise.
+int cxxrtl_commit(cxxrtl_handle handle);
+
// Simulate the design to a fixed point.
//
// Returns the number of delta cycles.