First video mixing working (hacky)

diff --git a/milkymist/dvisampler/analysis.py b/milkymist/dvisampler/analysis.py
index 4361f0abe7051b940f8ba49ab1337f3d9eeb1ddd..d402ce0853669bd9d19e9302fc1e4f223c586ec1 100644 (file)
--- a/milkymist/dvisampler/analysis.py
+++ b/milkymist/dvisampler/analysis.py
@@ -136,7 +136,7 @@ class FrameExtraction(Module):
                        vsync_r.eq(self.vsync)
                ]
 
-               fifo = AsyncFIFO(layout_len(frame_layout), 256)
+               fifo = AsyncFIFO(layout_len(frame_layout), 512)
                self.add_submodule(fifo, {"write": "pix", "read": "sys"})
                self.comb += [
                        fifo.we.eq(fifo_stb),

diff --git a/milkymist/framebuffer/lib.py b/milkymist/framebuffer/lib.py
index e85ed9df10a75ed74b6eddf506e0a216a5578b14..7fa5c9bd92fc5128df925e42cc74db99c4d70a0a 100644 (file)
--- a/milkymist/framebuffer/lib.py
+++ b/milkymist/framebuffer/lib.py
@@ -129,7 +129,7 @@ class FIFO(Module):
                ###
 
                data_width = 2+2*3*bpc_dac
-               fifo = AsyncFIFO(data_width, 256)
+               fifo = AsyncFIFO(data_width, 512)
                self.add_submodule(fifo, {"write": "sys", "read": "vga"})
                fifo_in = self.dac.payload
                fifo_out = Record(dac_layout)

diff --git a/top.py b/top.py
index 7adb852aea5bb37966a00f68ec78c6184cf44b33..029a02fd0dca23c79a29535d20ffa82161939bff 100644 (file)
--- a/top.py
+++ b/top.py
@@ -13,7 +13,7 @@ from cif import get_macros
 
 version = get_macros("common/version.h")["VERSION"][1:-1]
 
-clk_freq = (83 + Fraction(1, 3))*1000000
+clk_freq = (62 + Fraction(1, 2))*1000000
 sram_size = 4096 # in bytes
 l2_size = 8192 # in bytes
 
@@ -93,10 +93,10 @@ class SoC(Module):
                #
                self.submodules.asmicon = asmicon.ASMIcon(sdram_phy, sdram_geom, sdram_timing)
                asmiport_wb = self.asmicon.hub.get_port()
-               asmiport_fb0 = self.asmicon.hub.get_port(2)
-               asmiport_fb1 = self.asmicon.hub.get_port(2)
-               asmiport_dvi0 = self.asmicon.hub.get_port(2)
-               asmiport_dvi1 = self.asmicon.hub.get_port(2)
+               asmiport_fb0 = self.asmicon.hub.get_port(4)
+               asmiport_fb1 = self.asmicon.hub.get_port(4)
+               asmiport_dvi0 = self.asmicon.hub.get_port(4)
+               asmiport_dvi1 = self.asmicon.hub.get_port(4)
                self.asmicon.finalize()
                
                #