make dz consistent in SVP64

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index 57f55fd0f3b4b2544a28b8a53e8e98f68078678b..49341eaa7795919c8c2e32c4d8037e0d286d35c1 100644 (file)
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -127,7 +127,7 @@ The table for [[sv/svp64]] for `immed(RA)` is:
 
 | 0-1 |  2  |  3   4  |  description              |
 | --- | --- |---------|-------------------------- |
-| 00  | els |  sz  dz | normal mode               |
+| 00  | els |  dz  sz | normal mode               |
 | 01  | inv | CR-bit  | Rc=1: ffirst CR sel       |
 | 01  | inv | els RC1 |  Rc=0: ffirst z/nonz      |
 | 10  |   N | dz  els |  sat mode: N=0/1 u/s      |
@@ -165,11 +165,11 @@ The modes for `RA+RB` indexed version are slightly different:
 
 | 0-1 |  2  |  3   4  |  description              |
 | --- | --- |---------|-------------------------- |
-| 00  |   0 |  sz  dz | normal mode                      |
+| 00  |   0 |  dz  sz | normal mode                      |
 | 00  |   1 |  rsvd   | reserved                     |
 | 01  | inv | CR-bit  | Rc=1: ffirst CR sel              |
 | 01  | inv | dz  RC1 |  Rc=0: ffirst z/nonz |
-| 10  |   N | sz   dz |  sat mode: N=0/1 u/s |
+| 10  |   N | dz   sz |  sat mode: N=0/1 u/s |
 | 11  | inv | CR-bit  |  Rc=1: pred-result CR sel |
 | 11  | inv | dz  RC1 |  Rc=0: pred-result z/nonz |
 

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 6d79709b7fd53b4a3d42ca909fcbf19dced550d8..9de64d899b84e7b22da32edd9d9af2b686bd643d 100644 (file)
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -202,12 +202,12 @@ The Mode table for operations except LD/ST is laid out as follows:
 
 | 0-1 |  2  |  3   4  |  description              |
 | --- | --- |---------|-------------------------- |
-| 00  |   0 |  sz  dz | normal mode                      |
+| 00  |   0 |  dz  sz | normal mode                      |
 | 00  |   1 | dz CRM  | reduce mode (mapreduce), SUBVL=1 |
 | 00  |   1 | SVM CRM | subvector reduce mode, SUBVL>1   |
 | 01  | inv | CR-bit  | Rc=1: ffirst CR sel              |
 | 01  | inv | dz  RC1 |  Rc=0: ffirst z/nonz |
-| 10  |   N | sz   dz |  sat mode: N=0/1 u/s |
+| 10  |   N | dz   sz |  sat mode: N=0/1 u/s |
 | 11  | inv | CR-bit  |  Rc=1: pred-result CR sel |
 | 11  | inv | dz  RC1 |  Rc=0: pred-result z/nonz |