(no commit message)

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index df71ba5c3fbf0ba8d045bf7237131b5290a5ae57..0053bf3af927880e8ab763866b873e9a75f56a13 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -194,7 +194,7 @@ augmented to 7 bits in length.
 
 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing. 
 
-## RM-2P-1S1D
+## RM-2P-1S1D/2S
 
 | Field Name | Field bits | Description                 |
 |------------|------------|----------------------------|
@@ -205,6 +205,8 @@ Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or in
 
 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing. 
 
+`RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
+
 ## RM-2P-2S1D/1S2D
 
 The primary purpose for this encoding is for Twin Predication on LOAD