slicc: support for multiple cache entry types in the same state machine

To have multiple Entry types (e.g., a cache Entry type and
a directory Entry type), just declare one of them as a secondary
type by using the pair 'main="false"', e.g.:

  structure(DirEntry, desc="...", interface="AbstractCacheEntry",
            main="false") {

...and the primary type would be declared:

  structure(Entry, desc="...", interface="AbstractCacheEntry") {

diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py
index 8a4d7d9b541eff5c5c59c05a8e26ae59c12163a1..e90abaf440b58d2eff396f32963e9bdbbf97bb2e 100644 (file)
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -144,10 +144,13 @@ class StateMachine(Symbol):
             self.TBEType = type
 
         elif "interface" in type and "AbstractCacheEntry" == type["interface"]:
-            if self.EntryType != None:
-                self.error("Multiple AbstractCacheEntry types in a " \
-                           "single machine.");
-            self.EntryType = type
+            if "main" in type and "false" == type["main"].lower():
+                pass # this isn't the EntryType
+            else:
+                if self.EntryType != None:
+                    self.error("Multiple AbstractCacheEntry types in a " \
+                               "single machine.");
+                self.EntryType = type
 
     # Needs to be called before accessing the table
     def buildTable(self):