target_attr_10.c: Add -mcpu=generic.

2017-08-06  Andrew Pinski  <apinski@cavium.com>

        * gcc.target/aarch64/target_attr_10.c: Add -mcpu=generic.
        * gcc.target/aarch64/target_attr_13.c: LIkewise.
        * gcc.target/aarch64/target_attr_15.c: LIkewise.
        * gcc.target/aarch64/target_attr_4.c: Likewise.
        * gcc.target/aarch64/target_attr_1.c: Add -march=armv8-a.
        * gcc.target/aarch64/target_attr_2.c: Likewise.
        * gcc.target/aarch64/target_attr_7.c: Likewise.
        * gcc.target/aarch64/target_attr_crypto_ice_1.c: Likewise.
        * gcc.target/aarch64/target_attr_crypto_ice_2.c: Likewise.
        * gcc.target/aarch64/target_attr_3.c: Add -mcpu=generic -march=armv8-a.

From-SVN: r250904

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index a6a2798e916da97cab45fa17dc967c18debc1297..7d5352b3e29a89bd764997fdd50a874fa82d8112 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,16 @@
+2017-08-06  Andrew Pinski  <apinski@cavium.com>
+
+       * gcc.target/aarch64/target_attr_10.c: Add -mcpu=generic.
+       * gcc.target/aarch64/target_attr_13.c: LIkewise.
+       * gcc.target/aarch64/target_attr_15.c: LIkewise.
+       * gcc.target/aarch64/target_attr_4.c: Likewise.
+       * gcc.target/aarch64/target_attr_1.c: Add -march=armv8-a.
+       * gcc.target/aarch64/target_attr_2.c: Likewise.
+       * gcc.target/aarch64/target_attr_7.c: Likewise.
+       * gcc.target/aarch64/target_attr_crypto_ice_1.c: Likewise.
+       * gcc.target/aarch64/target_attr_crypto_ice_2.c: Likewise.
+       * gcc.target/aarch64/target_attr_3.c: Add -mcpu=generic -march=armv8-a.
+
 2017-08-06  Andrew Pinski  <apinski@cavium.com>
 
        * gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c: Pass

diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_1.c b/gcc/testsuite/gcc.target/aarch64/target_attr_1.c
index 0527d0c3d613ca696f63161e54d46cc0060b30fb..4a3a1ee233a0e276d114b380651c290afcd52c44 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/target_attr_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/target_attr_1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -mcpu=thunderx -dA" } */
+/* { dg-options "-O2 -mcpu=thunderx -march=armv8-a -dA" } */
 
 /* Test that cpu attribute overrides the command-line -mcpu.  */
 

diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_10.c b/gcc/testsuite/gcc.target/aarch64/target_attr_10.c
index 6d0577178f0b5ca57e84643ee31aea8ca6486f77..1849904711258fe182cfd30d616c25f650df43ed 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/target_attr_10.c
+++ b/gcc/testsuite/gcc.target/aarch64/target_attr_10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=armv8-a+simd" } */
+/* { dg-options "-O2 -march=armv8-a+simd -mcpu=generic" } */
 
 /* Using a SIMD intrinsic from a function tagged with nosimd should fail
    due to inlining rules.  */

diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_13.c b/gcc/testsuite/gcc.target/aarch64/target_attr_13.c
index 0f81e9aa587dce0986929e2ef719f07902a479af..d5bee3a7b900bf9348c9cbfd67f487c381b13bf6 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/target_attr_13.c
+++ b/gcc/testsuite/gcc.target/aarch64/target_attr_13.c
@@ -1,5 +1,5 @@
 /* { dg-do assemble } */
-/* { dg-options "-O2 -march=armv8-a+crc+crypto" } */
+/* { dg-options "-O2 -march=armv8-a+crc+crypto -mcpu=generic" } */
 
 #include "arm_acle.h"
 

diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_15.c b/gcc/testsuite/gcc.target/aarch64/target_attr_15.c
index 2d8c7b955ce3f7adb75e73f7c93e6c2f8772f133..108b372e4cc38b6e04e0fda149dd02b91d354246 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/target_attr_15.c
+++ b/gcc/testsuite/gcc.target/aarch64/target_attr_15.c
@@ -1,5 +1,5 @@
 /* { dg-do assemble } */
-/* { dg-options "-march=armv8-a+crypto -save-temps" } */
+/* { dg-options "-march=armv8-a+crypto -mcpu=generic -save-temps" } */
 
 /* Check that "+nothing" clears the ISA flags.  */
 

diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_2.c b/gcc/testsuite/gcc.target/aarch64/target_attr_2.c
index 39bb6e7dd364c173993e6e363b5d11321380642a..f84342d889f60a0d0ed09dda6ee7fc147f83e8a3 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/target_attr_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/target_attr_2.c
@@ -1,5 +1,5 @@
 /* { dg-do assemble } */
-/* { dg-options "-O2 -mcpu=cortex-a57 -ftree-vectorize -fdump-tree-vect-all" } */
+/* { dg-options "-O2 -mcpu=cortex-a57 -march=armv8-a -ftree-vectorize -fdump-tree-vect-all" } */
 
 /* The various ways to turn off simd availability should
    turn off vectorization.  */

diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_3.c b/gcc/testsuite/gcc.target/aarch64/target_attr_3.c
index 9f9c27654f6cfcceb65f32d1c4cf3f8fd8b13bfb..eacec5a655298dab09901b6c235dd978bc66cdf5 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/target_attr_3.c
+++ b/gcc/testsuite/gcc.target/aarch64/target_attr_3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -mno-fix-cortex-a53-835769 -save-temps" } */
+/* { dg-options "-O2 -mno-fix-cortex-a53-835769 -march=armv8-a -mcpu=generic -save-temps" } */
 
 /* Check that the attribute overrides the command line option
    and the fix is applied once.  */

diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_4.c b/gcc/testsuite/gcc.target/aarch64/target_attr_4.c
index d98ba42303f73f2afbe793499793359f615fd2f2..e0114084800cbb6b5abcdcd34f194fd0993ea02d 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/target_attr_4.c
+++ b/gcc/testsuite/gcc.target/aarch64/target_attr_4.c
@@ -1,5 +1,5 @@
 /* { dg-do assemble } */
-/* { dg-options "-O2 -march=armv8-a+nocrc -save-temps" } */
+/* { dg-options "-O2 -march=armv8-a+nocrc -mcpu=generic -save-temps" } */
 
 #include "arm_acle.h"
 

diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_7.c b/gcc/testsuite/gcc.target/aarch64/target_attr_7.c
index 818d327705f3d5ec7863da93c4181cc1441f58f5..6067ffed30ec2b2a0ab28be994f42d30c9829ad8 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/target_attr_7.c
+++ b/gcc/testsuite/gcc.target/aarch64/target_attr_7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -mcpu=thunderx -dA" } */
+/* { dg-options "-O2 -mcpu=thunderx -march=armv8-a -dA" } */
 
 /* Make sure that #pragma overrides command line option and
    target attribute overrides the pragma.  */

diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c
index 42f14c461a21c35850793e2c08093a8abae2c0a5..c74cc900f98d50bc8815784a3c9642dc2685d3a8 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -mcpu=thunderx+nofp" } */
+/* { dg-options "-O2 -mcpu=thunderx+nofp -march=armv8-a" } */
 
 #include "arm_neon.h"
 

diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c
index d6e7b6818325003051ee3afb5e497876930d8d26..d0a62b83351b671d157ec0de083d681394056d79 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -mcpu=thunderx+nofp" } */
+/* { dg-options "-O2 -mcpu=thunderx+nofp -march=armv8-a" } */
 
 /* Make sure that we don't ICE when dealing with vector parameters
    in a simd-tagged function within a non-simd translation unit.  */