Export('SimObject')
Export('SwigSource')
+########################################################################
+#
+# Trace Flags
+#
+all_flags = {}
+trace_flags = []
+def TraceFlag(name, desc=''):
+ if name in all_flags:
+ raise AttributeError, "Flag %s already specified" % name
+ flag = (name, (), desc)
+ trace_flags.append(flag)
+ all_flags[name] = ()
+
+def CompoundFlag(name, flags, desc=''):
+ if name in all_flags:
+ raise AttributeError, "Flag %s already specified" % name
+
+ compound = tuple(flags)
+ for flag in compound:
+ if flag not in all_flags:
+ raise AttributeError, "Trace flag %s not found" % flag
+ if all_flags[flag]:
+ raise AttributeError, \
+ "Compound flag can't point to another compound flag"
+
+ flag = (name, compound, desc)
+ trace_flags.append(flag)
+ all_flags[name] = compound
+
+Export('TraceFlag')
+Export('CompoundFlag')
+
########################################################################
#
# Set some compiler variables
env.Command('swig/init.cc', swig_modules, generate.makeSwigInit)
Source('swig/init.cc')
+# Generate traceflags.py
+flags = [ Value(f) for f in trace_flags ]
+env.Command('base/traceflags.py', flags, generate.traceFlagsPy)
+PySource('m5', 'base/traceflags.py')
+
+env.Command('base/traceflags.hh', flags, generate.traceFlagsHH)
+env.Command('base/traceflags.cc', flags, generate.traceFlagsCC)
+Source('base/traceflags.cc')
+
# Build the zip file
py_compiled = []
py_zip_depends = []
for f in isa_desc_files:
if not f.path.endswith('.hh'):
Source(f)
+
+ TraceFlag('Context')
SimObject('MipsTLB.py')
+ TraceFlag('MipsPRA')
+
if env['FULL_SYSTEM']:
#Insert Full-System Files Here
pass
Source('utility.cc')
SimObject('SparcTLB.py')
+ TraceFlag('Sparc')
if env['FULL_SYSTEM']:
SimObject('SparcSystem.py')
Source('utility.cc')
SimObject('X86TLB.py')
+ TraceFlag('Predecoder')
+ TraceFlag('X86')
if env['FULL_SYSTEM']:
SimObject('X86System.py')
Import('*')
-def make_cc(target, source, env):
- assert(len(source) == 1)
- assert(len(target) == 1)
-
- traceflags = {}
- execfile(str(source[0]), traceflags)
- func = traceflags['gen_cc']
- func(str(target[0]))
-
-def make_hh(target, source, env):
- assert(len(source) == 1)
- assert(len(target) == 1)
-
- traceflags = {}
- execfile(str(source[0]), traceflags)
- func = traceflags['gen_hh']
- func(str(target[0]))
-
-env.Command('traceflags.hh', 'traceflags.py', make_hh)
-env.Command('traceflags.cc', 'traceflags.py', make_cc)
-
Source('annotate.cc')
Source('bigint.cc')
Source('circlebuf.cc')
Source('str.cc')
Source('time.cc')
Source('trace.cc')
-Source('traceflags.cc')
Source('userinfo.cc')
Source('compression/lzss_compression.cc')
Source('mysql.cc')
Source('stats/mysql.cc')
-PySource('m5', 'traceflags.py')
+TraceFlag('Annotate')
+TraceFlag('GDBAcc')
+TraceFlag('GDBExtra')
+TraceFlag('GDBMisc')
+TraceFlag('GDBRead')
+TraceFlag('GDBRecv')
+TraceFlag('GDBSend')
+TraceFlag('GDBWrite')
+TraceFlag('SQL')
+TraceFlag('StatEvents')
+
+CompoundFlag('GDBAll', [ 'GDBMisc', 'GDBAcc', 'GDBRead', 'GDBWrite', 'GDBSend',
+ 'GDBRecv', 'GDBExtra' ])
'DiskImageRead',
'DiskImageWrite',
'DynInst',
- 'Ethernet',
- 'EthernetCksum',
- 'EthernetDMA',
- 'EthernetData',
- 'EthernetDesc',
- 'EthernetEEPROM',
- 'EthernetIntr',
- 'EthernetPIO',
- 'EthernetSM',
'Event',
'ExecEnable',
'ExecCPSeq',
if env['USE_CHECKER']:
Source('checker/cpu.cc')
+ TraceFlag('Checker')
checker_supports = False
for i in CheckerSupportedCPUList:
if i in env['CPU_MODELS']:
print i,
print ", please set USE_CHECKER=False or use one of those CPU models"
Exit(1)
+
+TraceFlag('Activity')
+TraceFlag('Commit')
+TraceFlag('Decode')
+TraceFlag('DynInst')
+TraceFlag('ExecEnable')
+TraceFlag('ExecCPSeq')
+TraceFlag('ExecEffAddr')
+TraceFlag('ExecFetchSeq')
+TraceFlag('ExecOpClass')
+TraceFlag('ExecRegDelta')
+TraceFlag('ExecResult')
+TraceFlag('ExecSpeculative')
+TraceFlag('ExecSymbol')
+TraceFlag('ExecThread')
+TraceFlag('ExecTicks')
+TraceFlag('Fetch')
+TraceFlag('IntrControl')
+TraceFlag('PCEvent')
+TraceFlag('Quiesce')
+
+CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
+ 'ExecEffAddr', 'ExecResult', 'ExecSymbol' ])
SimObject('MemTest.py')
Source('memtest.cc')
+
+ TraceFlag('MemTest')
Import('*')
+if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']:
+ Source('2bit_local_pred.cc')
+ Source('btb.cc')
+ Source('ras.cc')
+ Source('tournament_pred.cc')
+
+ TraceFlag('CommitRate')
+ TraceFlag('IEW')
+ TraceFlag('IQ')
+
if 'O3CPU' in env['CPU_MODELS']:
SimObject('FUPool.py')
SimObject('FuncUnitConfig.py')
Source('scoreboard.cc')
Source('store_set.cc')
+ TraceFlag('FreeList')
+ TraceFlag('LSQ')
+ TraceFlag('LSQUnit')
+ TraceFlag('MemDepUnit')
+ TraceFlag('O3CPU')
+ TraceFlag('ROB')
+ TraceFlag('Rename')
+ TraceFlag('Scoreboard')
+ TraceFlag('StoreSet')
+ TraceFlag('Writeback')
+
+ CompoundFlag('O3CPUAll', [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit',
+ 'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit',
+ 'DynInst', 'O3CPU', 'Activity', 'Scoreboard', 'Writeback' ])
+
if env['TARGET_ISA'] == 'alpha':
Source('alpha/cpu.cc')
Source('alpha/cpu_builder.cc')
if env['USE_CHECKER']:
SimObject('O3Checker.py')
Source('checker_builder.cc')
-
-if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']:
- Source('2bit_local_pred.cc')
- Source('btb.cc')
- Source('ras.cc')
- Source('tournament_pred.cc')
-
Source('lw_back_end.cc')
Source('lw_lsq.cc')
Source('rename_table.cc')
+
+ TraceFlag('BE')
+ TraceFlag('FE')
+ TraceFlag('IBE')
+ TraceFlag('OzoneCPU')
+ TraceFlag('OzoneLSQ')
+
+ CompoundFlag('OzoneCPUAll', [ 'BE', 'FE', 'IBE', 'OzoneLSQ', 'OzoneCPU' ])
+
if env['USE_CHECKER']:
SimObject('OzoneChecker.py')
Source('checker_builder.cc')
SimObject('TimingSimpleCPU.py')
Source('timing.cc')
+if 'AtomicSimpleCPU' in env['CPU_MODELS'] or \
+ 'TimingSimpleCPU' in env['CPU_MODELS']:
+ TraceFlag('SimpleCPU')
+
if need_simple_base:
Source('base.cc')
Source('sinic.cc')
Source('uart.cc')
Source('uart8250.cc')
+
+ TraceFlag('Console')
+ TraceFlag('ConsoleVerbose')
+ TraceFlag('DiskImageRead')
+ TraceFlag('DiskImageWrite')
+ TraceFlag('DMA')
+ TraceFlag('Ethernet')
+ TraceFlag('EthernetCksum')
+ TraceFlag('EthernetDMA')
+ TraceFlag('EthernetData')
+ TraceFlag('EthernetDesc')
+ TraceFlag('EthernetEEPROM')
+ TraceFlag('EthernetIntr')
+ TraceFlag('EthernetPIO')
+ TraceFlag('EthernetSM')
+ TraceFlag('IdeCtrl')
+ TraceFlag('IdeDisk')
+ TraceFlag('IsaFake')
+ TraceFlag('PCIDEV')
+ TraceFlag('PciConfigAll')
+ TraceFlag('SimpleDisk')
+ TraceFlag('SimpleDiskData')
+ TraceFlag('Uart')
+
+ CompoundFlag('DiskImageAll', [ 'DiskImageRead', 'DiskImageWrite' ])
+ CompoundFlag('EthernetAll', [ 'Ethernet', 'EthernetPIO', 'EthernetDMA',
+ 'EthernetData' , 'EthernetDesc', 'EthernetIntr', 'EthernetSM',
+ 'EthernetCksum' ])
+ CompoundFlag('EthernetNoData', [ 'Ethernet', 'EthernetPIO', 'EthernetDesc',
+ 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ])
+ CompoundFlag('IdeAll', [ 'IdeCtrl', 'IdeDisk' ])
+
Source('tsunami_cchip.cc')
Source('tsunami_io.cc')
Source('tsunami_pchip.cc')
+
+ TraceFlag('AlphaConsole')
+ TraceFlag('MC146818')
+ TraceFlag('Tsunami')
warn("Device %s accessed by read to address %#x size=%d\n",
name(), pkt->getAddr(), pkt->getSize());
if (params()->ret_bad_addr) {
- DPRINTF(Tsunami, "read to bad address va=%#x size=%d\n",
+ DPRINTF(IsaFake, "read to bad address va=%#x size=%d\n",
pkt->getAddr(), pkt->getSize());
pkt->setBadAddress();
} else {
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
- DPRINTF(Tsunami, "read va=%#x size=%d\n",
+ DPRINTF(IsaFake, "read va=%#x size=%d\n",
pkt->getAddr(), pkt->getSize());
switch (pkt->getSize()) {
case sizeof(uint64_t):
name(), pkt->getAddr(), pkt->getSize(), data);
}
if (params()->ret_bad_addr) {
- DPRINTF(Tsunami, "write to bad address va=%#x size=%d \n",
+ DPRINTF(IsaFake, "write to bad address va=%#x size=%d \n",
pkt->getAddr(), pkt->getSize());
pkt->setBadAddress();
} else {
- DPRINTF(Tsunami, "write - va=%#x size=%d \n",
+ DPRINTF(IsaFake, "write - va=%#x size=%d \n",
pkt->getAddr(), pkt->getSize());
if (params()->update_data) {
return dynamic_cast<const Params *>(_params);
}
/**
- * The constructor for Tsunmami Fake just registers itself with the MMU.
+ * The constructor for Isa Fake just registers itself with the MMU.
* @param p params structure
*/
IsaFake(Params *p);
Source('iob.cc')
Source('t1000.cc')
Source('mm_disk.cc')
+
+ TraceFlag('Iob')
Source('kernel_stats.cc')
Source('system_events.cc')
+ TraceFlag('DebugPrintf')
+ TraceFlag('Printf')
+
Source('linux/events.cc')
Source('linux/linux_syscalls.cc')
Source('linux/printk.cc')
Source('tru64/printf.cc')
Source('tru64/tru64_events.cc')
Source('tru64/tru64_syscalls.cc')
+ TraceFlag('BADADDR')
+
else:
Source('page_table.cc')
Source('translating_port.cc')
+
+TraceFlag('Bus')
+TraceFlag('BusAddrRanges')
+TraceFlag('BusBridge')
+TraceFlag('LLSC')
+TraceFlag('MMU')
+TraceFlag('MemoryAccess')
Source('base_cache.cc')
Source('cache.cc')
Source('cache_builder.cc')
+
+TraceFlag('Cache')
+TraceFlag('CachePort')
+TraceFlag('CacheRepl')
+TraceFlag('HWPrefetch')
SimObject('Repl.py')
Source('repl/gen.cc')
+
+TraceFlag('IIC')
+TraceFlag('IICMore')
+TraceFlag('Split')
arcname = py_compiled[zipname].arcname
zf.write(zipname, arcname)
zf.close()
+
+ def traceFlagsPy(self, target, source, env):
+ assert(len(target) == 1)
+
+ f = file(str(target[0]), 'w')
+
+ allFlags = []
+ for s in source:
+ val = eval(s.get_contents())
+ allFlags.append(val)
+
+ print >>f, 'baseFlags = ['
+ for flag, compound, desc in allFlags:
+ if not compound:
+ print >>f, " '%s'," % flag
+ print >>f, " ]"
+ print >>f
+
+ print >>f, 'compoundFlags = ['
+ print >>f, " 'All',"
+ for flag, compound, desc in allFlags:
+ if compound:
+ print >>f, " '%s'," % flag
+ print >>f, " ]"
+ print >>f
+
+ print >>f, "allFlags = frozenset(baseFlags + compoundFlags)"
+ print >>f
+
+ print >>f, 'compoundFlagMap = {'
+ all = tuple([flag for flag,compound,desc in allFlags if not compound])
+ print >>f, " 'All' : %s," % (all, )
+ for flag, compound, desc in allFlags:
+ if compound:
+ print >>f, " '%s' : %s," % (flag, compound)
+ print >>f, " }"
+ print >>f
+
+ print >>f, 'flagDescriptions = {'
+ print >>f, " 'All' : 'All flags',"
+ for flag, compound, desc in allFlags:
+ print >>f, " '%s' : '%s'," % (flag, desc)
+ print >>f, " }"
+
+ f.close()
+
+ def traceFlagsCC(self, target, source, env):
+ assert(len(target) == 1)
+
+ f = file(str(target[0]), 'w')
+
+ allFlags = []
+ for s in source:
+ val = eval(s.get_contents())
+ allFlags.append(val)
+
+ # file header
+ print >>f, '''
+/*
+ * DO NOT EDIT THIS FILE! Automatically generated
+ */
+
+#include "base/traceflags.hh"
+
+using namespace Trace;
+
+const char *Trace::flagStrings[] =
+{'''
+
+ # The string array is used by SimpleEnumParam to map the strings
+ # provided by the user to enum values.
+ for flag, compound, desc in allFlags:
+ if not compound:
+ print >>f, ' "%s",' % flag
+
+ print >>f, ' "All",'
+ for flag, compound, desc in allFlags:
+ if compound:
+ print >>f, ' "%s",' % flag
+
+ print >>f, '};'
+ print >>f
+ print >>f, 'const int Trace::numFlagStrings = %d;' % len(allFlags)
+ print >>f
+
+ #
+ # Now define the individual compound flag arrays. There is an array
+ # for each compound flag listing the component base flags.
+ #
+ all = tuple([flag for flag,compound,desc in allFlags if not compound])
+ print >>f, 'static const Flags AllMap[] = {'
+ for flag, compound, desc in allFlags:
+ if not compound:
+ print >>f, " %s," % flag
+ print >>f, '};'
+ print >>f
+
+ for flag, compound, desc in allFlags:
+ if not compound:
+ continue
+ print >>f, 'static const Flags %sMap[] = {' % flag
+ for flag in compound:
+ print >>f, " %s," % flag
+ print >>f, " (Flags)-1"
+ print >>f, '};'
+ print >>f
+
+ #
+ # Finally the compoundFlags[] array maps the compound flags
+ # to their individual arrays/
+ #
+ print >>f, 'const Flags *Trace::compoundFlags[] ='
+ print >>f, '{'
+ print >>f, ' AllMap,'
+ for flag, compound, desc in allFlags:
+ if compound:
+ print >>f, ' %sMap,' % flag
+ # file trailer
+ print >>f, '};'
+
+ f.close()
+
+ def traceFlagsHH(self, target, source, env):
+ assert(len(target) == 1)
+
+ f = file(str(target[0]), 'w')
+
+ allFlags = []
+ for s in source:
+ val = eval(s.get_contents())
+ allFlags.append(val)
+
+ # file header boilerplate
+ print >>f, '''
+/*
+ * DO NOT EDIT THIS FILE!
+ *
+ * Automatically generated from traceflags.py
+ */
+
+#ifndef __BASE_TRACE_FLAGS_HH__
+#define __BASE_TRACE_FLAGS_HH__
+
+namespace Trace {
+
+enum Flags {'''
+
+ # Generate the enum. Base flags come first, then compound flags.
+ idx = 0
+ for flag, compound, desc in allFlags:
+ if not compound:
+ print >>f, ' %s = %d,' % (flag, idx)
+ idx += 1
+
+ numBaseFlags = idx
+ print >>f, ' NumFlags = %d,' % idx
+
+ # put a comment in here to separate base from compound flags
+ print >>f, '''
+// The remaining enum values are *not* valid indices for Trace::flags.
+// They are "compound" flags, which correspond to sets of base
+// flags, and are used by changeFlag.'''
+
+ print >>f, ' All = %d,' % idx
+ idx += 1
+ for flag, compound, desc in allFlags:
+ if compound:
+ print >>f, ' %s = %d,' % (flag, idx)
+ idx += 1
+
+ numCompoundFlags = idx - numBaseFlags
+ print >>f, ' NumCompoundFlags = %d' % numCompoundFlags
+
+ # trailer boilerplate
+ print >>f, '''\
+}; // enum Flags
+
+// Array of strings for SimpleEnumParam
+extern const char *flagStrings[];
+extern const int numFlagStrings;
+
+// Array of arraay pointers: for each compound flag, gives the list of
+// base flags to set. Inidividual flag arrays are terminated by -1.
+extern const Flags *compoundFlags[];
+
+/* namespace Trace */ }
+
+#endif // __BASE_TRACE_FLAGS_HH__
+'''
+
+ f.close()
Source('process.cc')
Source('syscall_emul.cc')
+
+TraceFlag('Config')
+TraceFlag('Event')
+TraceFlag('Fault')
+TraceFlag('Flow')
+TraceFlag('IPI')
+TraceFlag('IPR')
+TraceFlag('Interrupt')
+TraceFlag('Loader')
+TraceFlag('Stack')
+TraceFlag('SyscallVerbose')
+TraceFlag('TLB')
+TraceFlag('Thread')
+TraceFlag('Timer')
+TraceFlag('VtoPhys')
projects / gem5.git / commitdiff