wire up missing register bits.

Not sure how they went missing...but just noticed them.

diff --git a/litex/soc/cores/i2s.py b/litex/soc/cores/i2s.py
index a5dde4ca5cc4cb6b8877cbad25afed7664e020c0..7843568399fbc60b39fc2f143a733d6e8eaa9c8f 100644 (file)
--- a/litex/soc/cores/i2s.py
+++ b/litex/soc/cores/i2s.py
@@ -283,10 +283,12 @@ class S7I2S(Module, AutoCSR, AutoDoc):
                 o_WRERR       = rx_wrerr,
             )
             self.comb += [  # Wire up the status signals and interrupts
+                self.rx_stat.fields.overflow.eq(rx_wrerr),
                 self.rx_stat.fields.underflow.eq(rx_rderr),
                 self.rx_stat.fields.dataready.eq(rx_almostfull),
                 self.rx_stat.fields.wrcount.eq(rx_wrcount),
                 self.rx_stat.fields.rdcount.eq(rx_rdcount),
+                self.rx_stat.fields.empty.eq(rx_empty),
                 self.ev.rx_ready.trigger.eq(rx_almostfull),
                 self.ev.rx_error.trigger.eq(rx_wrerr | rx_rderr),
             ]