Clean verilog code from not used define block

diff --git a/tests/xilinx/shifter.v b/tests/xilinx/shifter.v
index c55632552a4c36f647143cf7ef51cbeec87acf94..04ae49d831f89b11863e1a6cde708b0b6d8a638e 100644 (file)
--- a/tests/xilinx/shifter.v
+++ b/tests/xilinx/shifter.v
@@ -9,14 +9,8 @@ in
 \r
     always @(posedge clk)\r
        begin\r
-`ifndef BUG\r
                out    <= out >> 1;\r
                out[7] <= in;\r
-`else\r
-\r
-               out    <= out << 1;\r
-               out[7] <= in;\r
-`endif\r
        end\r
 \r
 endmodule\r

diff --git a/tests/xilinx/tribuf.v b/tests/xilinx/tribuf.v
index 3fa6eb6c62134f5454cf90769a6b3389288a0d4e..75149d8ba2711a020fb9924ac886099ecb758929 100644 (file)
--- a/tests/xilinx/tribuf.v
+++ b/tests/xilinx/tribuf.v
@@ -2,15 +2,9 @@ module tristate (en, i, o);
     input en;
     input i;
     output reg o;
-`ifndef BUG 
     
     always @(en or i)
                o <= (en)? i : 1'bZ;
-`else
-       
-    always @(en or i)
-               o <= (en)? ~i : 1'bZ;
-`endif
 endmodule