TimingSimpleCPU: fix NO_ACCESS memory op handling

When a request is NO_ACCESS (x86 CDA microinstruction), the memory op
doesn't go to the cache, so TimingSimpleCPU::completeDataAccess needs
to handle the case where the current status of the CPU is Running
and not DcacheWaitResponse or DTBWaitResponse

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index b8fc5ab84614554330f6b5025bd3575a3dd6cf0a..8a53aac3a3aa634cea773b2c3c1762ae4ddc9f25 100644 (file)
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -868,6 +868,8 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
     // received a response from the dcache: complete the load or store
     // instruction
     assert(!pkt->isError());
+    assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
+           pkt->req->getFlags().isSet(Request::NO_ACCESS));
 
     numCycles += tickToCycles(curTick - previousTick);
     previousTick = curTick;
@@ -897,7 +899,6 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
         }
     }
 
-    assert(_status == DcacheWaitResponse || _status == DTBWaitResponse);
     _status = Running;
 
     Fault fault = curStaticInst->completeAcc(pkt, this, traceData);