boards: always define timing constraints the same way (1e9/freq_mhz)

diff --git a/litex/boards/platforms/genesys2.py b/litex/boards/platforms/genesys2.py
index 89f721205fcdd20292d94e417dd36c5e9be3ad2c..083ab085a5d313f6b3b1b2de4f35b6c517fa5ea9 100644 (file)
--- a/litex/boards/platforms/genesys2.py
+++ b/litex/boards/platforms/genesys2.py
@@ -118,6 +118,6 @@ class Platform(XilinxPlatform):
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
         try:
-            self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0)
+            self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6)
         except ConstraintError:
             pass

diff --git a/litex/boards/platforms/kc705.py b/litex/boards/platforms/kc705.py
index 498f3565c41d2363490b166ce06c7515e1477edb..3948e5add18e4c22a828b4c7d8180cf494e2289e 100644 (file)
--- a/litex/boards/platforms/kc705.py
+++ b/litex/boards/platforms/kc705.py
@@ -553,15 +553,15 @@ set_property CONFIG_VOLTAGE 2.5 [current_design]
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
         try:
-            self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
+            self.add_period_constraint(self.lookup_request("clk200").p, 1e9/200e6)
         except ConstraintError:
             pass
         try:
-            self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0)
+            self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6)
         except ConstraintError:
             pass
         try:
-            self.add_period_constraint(self.lookup_request("eth_clocks").tx, 8.0)
+            self.add_period_constraint(self.lookup_request("eth_clocks").tx, 1e9/125e6)
         except ConstraintError:
             pass
         if isinstance(self.toolchain, XilinxISEToolchain):

diff --git a/litex/boards/platforms/nexys_video.py b/litex/boards/platforms/nexys_video.py
index 0844cce9f69d038153912bafef49c50e0887977d..3ed2c0c15aa61f554d3edfad8913ad98808d38d4 100644 (file)
--- a/litex/boards/platforms/nexys_video.py
+++ b/litex/boards/platforms/nexys_video.py
@@ -239,6 +239,6 @@ class Platform(XilinxPlatform):
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
         try:
-            self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0)
+            self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6)
         except ConstraintError:
             pass

diff --git a/litex/boards/platforms/versa_ecp3.py b/litex/boards/platforms/versa_ecp3.py
index ca9b6bd03c7a525d72db49000b170e13ba1e30c4..045f4d10003cc0c9fa9a1e94c705cc5c40301337 100644 (file)
--- a/litex/boards/platforms/versa_ecp3.py
+++ b/litex/boards/platforms/versa_ecp3.py
@@ -85,11 +85,11 @@ class Platform(LatticePlatform):
     def do_finalize(self, fragment):
         LatticePlatform.do_finalize(self, fragment)
         try:
-            self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 8.0)
+            self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 1e9/125e6)
         except ConstraintError:
             pass
         try:
-            self.add_period_constraint(self.lookup_request("eth_clocks", 1).rx, 8.0)
+            self.add_period_constraint(self.lookup_request("eth_clocks", 1).rx, 1e9/125e6)
         except ConstraintError:
             pass
 

diff --git a/litex/boards/platforms/versa_ecp5.py b/litex/boards/platforms/versa_ecp5.py
index 7d11e47023a9f1433e005ed5a983fab5499f9d1f..8368efa7a052cfa9bc9b56afcded41150d8edc21 100644 (file)
--- a/litex/boards/platforms/versa_ecp5.py
+++ b/litex/boards/platforms/versa_ecp5.py
@@ -184,11 +184,11 @@ class Platform(LatticePlatform):
 
     def do_finalize(self, fragment):
         try:
-            self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 8.0)
+            self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 1e9/125e6)
         except ConstraintError:
             pass
         try:
-            self.add_period_constraint(self.lookup_request("eth_clocks", 1).rx, 8.0)
+            self.add_period_constraint(self.lookup_request("eth_clocks", 1).rx, 1e9/125e6)
         except ConstraintError:
             pass
 

diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py
index c5a20ea2d3a2ed55c9afe55e0750a66e59ab39da..c6e90e45ef8ba123a77b7c1a27e7e959e94cd08a 100755 (executable)
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@@ -104,8 +104,8 @@ class EthernetSoC(BaseSoC):
 
         self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
         self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 80.0)
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 80.0)
+        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6)
+        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6)
         self.platform.add_false_path_constraints(
             self.crg.cd_sys.clk,
             self.ethphy.crg.cd_eth_rx.clk,

diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py
index 150f830b538cb7d0bf1250d64048f3ecd9108f74..7c8c331b7a26ec516e819d5d6f92894eda578464 100755 (executable)
--- a/litex/boards/targets/genesys2.py
+++ b/litex/boards/targets/genesys2.py
@@ -95,8 +95,8 @@ class EthernetSoC(BaseSoC):
 
         self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
         self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0)
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0)
+        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
+        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
         self.platform.add_false_path_constraints(
             self.crg.cd_sys.clk,
             self.ethphy.crg.cd_eth_rx.clk,

diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py
index 0493db8c6112cb99cbcb6a5d4a9eb6a0bb02e5db..3ad91e76d774908cc45a3686af6a38f8364d82e2 100755 (executable)
--- a/litex/boards/targets/kc705.py
+++ b/litex/boards/targets/kc705.py
@@ -95,8 +95,8 @@ class EthernetSoC(BaseSoC):
 
         self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
         self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0)
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0)
+        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
+        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
         self.platform.add_false_path_constraints(
             self.crg.cd_sys.clk,
             self.ethphy.crg.cd_eth_rx.clk,

diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py
index db94b9f6343711497366a6f41c80e1e61d5b9676..1e58f831fb0b9581b248856efb3188416e27b6b6 100755 (executable)
--- a/litex/boards/targets/nexys_video.py
+++ b/litex/boards/targets/nexys_video.py
@@ -101,8 +101,8 @@ class EthernetSoC(BaseSoC):
 
         self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
         self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0)
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0)
+        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
+        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
         self.platform.add_false_path_constraints(
             self.crg.cd_sys.clk,
             self.ethphy.crg.cd_eth_rx.clk,

diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py
index 6331d4a1289b45272f860919ec3c00299753375c..e28ccb3e67064968002e4a0e3b48fcf4297ef8ac 100755 (executable)
--- a/litex/boards/targets/versa_ecp5.py
+++ b/litex/boards/targets/versa_ecp5.py
@@ -41,7 +41,7 @@ class _CRG(Module):
         # clk / rst
         clk100 = platform.request("clk100")
         rst_n = platform.request("rst_n")
-        platform.add_period_constraint(clk100, 10.0)
+        platform.add_period_constraint(clk100, 1e9/100e6)
 
         # power on reset
         por_count = Signal(16, reset=2**16-1)