ffAmuxAB -> ffAenpol

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index 9291c2dfb0b984442676970caac5160b8c78453e..16a098fd0bc07949da523c42e97217268ff847b7 100644 (file)
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -83,9 +83,10 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
                        A.replace(Q, D);
                        if (st.ffAmux) {
                                SigSpec Y = st.ffAmux->getPort("\\Y");
-                               SigSpec AB = st.ffAmux->getPort(st.ffAmuxAB == "\\A" ? "\\B" : "\\A");
+                               SigSpec AB = st.ffAmux->getPort(st.ffAenpol ? "\\A" : "\\B");
                                A.replace(Y, AB);
-                               cell->setPort("\\CEA2", st.ffAmux->getPort("\\S"));
+                               SigSpec S = st.ffAmux->getPort("\\S");
+                               cell->setPort("\\CEA2", st.ffAenpol ? S : pm.module->Not(NEW_ID, S));
                        }
                        else
                                cell->setPort("\\CEA2", State::S1);

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index fa490146c6279517bba18356e85b669d8873f2b3..5799358697b6df469f8afc19e59c8b7137e9d16a 100644 (file)
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -2,7 +2,8 @@ pattern xilinx_dsp
 
 state <SigBit> clock
 state <SigSpec> sigA sigffAmux sigB sigffBmux sigC sigM sigP
-state <IdString> ffAmuxAB ffBmuxAB ffMmuxAB ffPmuxAB postAddAB postAddMuxAB
+state <IdString> ffBmuxAB ffMmuxAB ffPmuxAB postAddAB postAddMuxAB
+state <bool> ffAenpol
 
 match dsp
        select dsp->type.in(\DSP48E1)
@@ -69,9 +70,10 @@ match ffAmux
        filter GetSize(port(ffAmux, \Y)) >= GetSize(sigA)
        slice offset GetSize(port(ffAmux, \Y))
        filter offset+GetSize(sigA) <= GetSize(port(ffAmux, \Y)) && port(ffAmux, \Y).extract(offset, GetSize(sigA)) == sigA
-       choice <IdString> AB {\A, \B}
-       filter offset+GetSize(sigffAmux) <= GetSize(port(ffAmux, \Y)) && port(ffAmux, AB).extract(offset, GetSize(sigffAmux)) == sigffAmux
-       set ffAmuxAB AB
+       choice <IdString> BA {\B, \A}
+       filter offset+GetSize(sigffAmux) <= GetSize(port(ffAmux, \Y)) && port(ffAmux, BA).extract(offset, GetSize(sigffAmux)) == sigffAmux
+       define <bool> pol (BA == \B)
+       set ffAenpol pol
        semioptional
 endmatch