synthetic instruction.
* gas/rx/r-bcc.d: Update expected disassembly of synthetic beq.a
instruction.
+2011-07-26 Kazuhiro Inaoka <kazuhiro.inaoka.ud@renesas.com>
+
+ * config/tc-rx.c (md_convert_frag): Fix encoding of beq.a
+ synthetic instruction.
+
2011-07-25 Tristan Gingold <gingold@adacore.com>
* frags.c (frag_grow): Simplify the code.
reloc_adjust = 1;
break;
case OPCODE (OT_beq, 5): /* BEQ.A - synthetic. */
- op[0] = 0x1e; /* bne.s .+4. */
+ op[0] = 0x1d; /* bne.s .+5. */
op[1] = 0x04; /* bra.a dsp:24. */
disp -= 1;
#if RX_OPCODE_BIG_ENDIAN
reloc_adjust = 1;
break;
case OPCODE (OT_bne, 5): /* BNE.A - synthetic. */
- op[0] = 0x15; /* beq.s .+4. */
+ op[0] = 0x15; /* beq.s .+5. */
op[1] = 0x04; /* bra.a dsp:24. */
disp -= 1;
#if RX_OPCODE_BIG_ENDIAN
+2011-07-26 Kazuhiro Inaoka <kazuhiro.inaoka.ud@renesas.com>
+
+ * gas/rx/r-bcc.d: Update expected disassembly of synthetic beq.a
+ instruction.
+
2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
Chao-ying Fu <fu@mips.com>
Richard Sandiford <rdsandiford@googlemail.com>
00000000 <beq>:
0: 20 32 beq\.b 32 <dsp8>
2: 3a 86 13 beq\.w 1388 <dsp16>
- 5: 1e bne\.s b <bne\+0x1>
+ 5: 1d bne\.s a <bne>
6: 04 1a a1 07 bra\.a 7a120 <dsp24>
0000000a <bne>: