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disable PLL so increase not-connected by another 4 pins
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 1 Apr 2021 22:24:00 +0000 (23:24 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 1 Apr 2021 22:24:00 +0000 (23:24 +0100)
libresoc/ls180.py patch | blob | history

diff --git a/libresoc/ls180.py b/libresoc/ls180.py
index 984755d2f87d22fb2fa8d723d0b12486f688ad2e..c9d10282655e1931faa0aabb6c1b0ec6ef494e3a 100644 (file)
--- a/libresoc/ls180.py
+++ b/libresoc/ls180.py
@@ -156,6 +156,7 @@ def io():
     num_nc += 4 # mspi1 comments out, litex problems 25mar2021
     num_nc += 6 # sd0 comments out, litex problems 25mar2021
     num_nc += 2 # pwm comments out, litex problems 25mar2021
+    num_nc += 4 # PLL disabled for now
     nc = ' '.join("NC%d" % i for i in range(num_nc))
     _io.append(("nc", 0, Pins(nc), IOStandard("LVCMOS33")))