configs: Unifiy interpretation of Realview mem_regions
authorGiacomo Travaglini <giacomo.travaglini@arm.com>
Mon, 4 Feb 2019 12:11:03 +0000 (12:11 +0000)
committerGiacomo Travaglini <giacomo.travaglini@arm.com>
Thu, 7 Feb 2019 12:59:11 +0000 (12:59 +0000)
In every arm platform which is making use of them, mem_regions are
interpreted as a pair of start address and size. However arm
SimpleSystem, which is using VExpress_GEM5_V1, is interpreting them as
start address and end address.  This patch is fixing this mismatch.

Change-Id: I0b2a2193cd07fbc5430f233438269a9c7c353df9
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16205
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

configs/example/arm/devices.py

index 15492cb9bc62962714c7fc8dbef5cc2fff82c92e..e2c8be8afc37ea13eb8a367666ef86c4ccb31caa 100644 (file)
@@ -207,8 +207,8 @@ class SimpleSystem(LinuxArmSystem):
         self.iobridge = Bridge(delay='50ns')
         # Device DMA -> MEM
         mem_range = self.realview._mem_regions[0]
-        mem_range_size = long(mem_range[1]) - long(mem_range[0])
-        assert mem_range_size >= long(Addr(mem_size))
+        max_size = long(mem_range[1])
+        assert max_size >= long(Addr(mem_size))
         self.mem_ranges = [ AddrRange(start=mem_range[0], size=mem_size) ]
         self._caches = caches
         if self._caches: