(no commit message)

diff --git a/simple_v_extension/specification/sv.setvl.mdwn b/simple_v_extension/specification/sv.setvl.mdwn
index 0c144fccf0ba0c88179b058ae2f48b4882520361..be7db76a9c4b8c39edc863f6fe8c2b6cdc81321f 100644 (file)
--- a/simple_v_extension/specification/sv.setvl.mdwn
+++ b/simple_v_extension/specification/sv.setvl.mdwn
@@ -7,7 +7,7 @@ Thus it makes more sense to actually *use* one of the scalar registers *as* VL.
 
 Format for Vector Configuration Instructions under OP-V major opcode:
 
-| 31|30...20|19....15|14..12|11 7|6.....0| name       |
+| 31|30...20|19....15|14..12|11.7|6.....0| name       |
 |---|-------|--------|------|----|-------|------------|
 | 0 | VLMAX | rs1    | 111  | rd |1010111| sv.setvl   |
 | 0 | VLMAX | 0 (x0) | 111  | rd |1010111| sv.setvl   |