aiger: -xaiger to read $_DFF_[NP]_ back with new clocks created

according to mergeability class, and init state as cell attr

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 6fda92d7322f26d0a6b21f0cecd25c9b899db2dc..7e5e6dd2daf5ef2dfeb560e23d84ec926646ea14 100644 (file)
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -454,6 +454,14 @@ void AigerReader::parse_xaiger()
                        for (unsigned i = 0; i < flopNum; i++)
                                mergeability.emplace_back(parse_xaiger_literal(f));
                }
+               else if (c == 's') {
+                       uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+                       flopNum = parse_xaiger_literal(f);
+                       log_assert(dataSize == (flopNum+1) * sizeof(uint32_t));
+                       initial_state.reserve(flopNum);
+                       for (unsigned i = 0; i < flopNum; i++)
+                               initial_state.emplace_back(parse_xaiger_literal(f));
+               }
                else if (c == 'n') {
                        parse_xaiger_literal(f);
                        f >> s;
@@ -767,6 +775,7 @@ void AigerReader::post_process()
                }
        }
 
+       dict<int, Wire*> mergeability_to_clock;
        for (uint32_t i = 0; i < flopNum; i++) {
                RTLIL::Wire *d = outputs[outputs.size() - flopNum + i];
                log_assert(d);
@@ -778,10 +787,22 @@ void AigerReader::post_process()
                log_assert(q->port_input);
                q->port_input = false;
 
-               auto ff = module->addCell(NEW_ID, ID($__ABC9_FF_));
+               Cell* ff;
+               int clock_index = mergeability[i];
+               if (clock_index < 0) {
+                       ff = module->addCell(NEW_ID, ID($_DFF_N_));
+                       clock_index = -clock_index;
+               }
+               else if (clock_index > 0)
+                       ff = module->addCell(NEW_ID, ID($_DFF_P_));
+               else log_abort();
+               auto r = mergeability_to_clock.insert(clock_index);
+               if (r.second)
+                       r.first->second = module->addWire(NEW_ID);
+               ff->setPort(ID::C, r.first->second);
                ff->setPort(ID::D, d);
                ff->setPort(ID::Q, q);
-               ff->attributes[ID::abc9_mergeability] = mergeability[i];
+               ff->attributes[ID::abc9_init] = initial_state[i];
        }
 
        dict<RTLIL::IdString, std::pair<int,int>> wideports_cache;

diff --git a/frontends/aiger/aigerparse.h b/frontends/aiger/aigerparse.h
index 46ac81212b4f8f8e60fb58372212198d1307a0a7..251a24977e297c4bfe7fed66178507dff4da6e08 100644 (file)
--- a/frontends/aiger/aigerparse.h
+++ b/frontends/aiger/aigerparse.h
@@ -45,7 +45,7 @@ struct AigerReader
     std::vector<RTLIL::Wire*> outputs;
     std::vector<RTLIL::Wire*> bad_properties;
     std::vector<RTLIL::Cell*> boxes;
-    std::vector<int> mergeability;
+    std::vector<int> mergeability, initial_state;
 
     AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports);
     void parse_aiger();