radv: set DISABLE_CONSTANT_ENCODE_REG to 1 for Raven2

Ported from RadeonSI, will be emitted for GFX10 too.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index e35ccf809565e9d7a819d36f5c9e9fe395d0959a..29f2e0c8a6050bbf4c43c7d1f6c0627636e2b571 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1876,6 +1876,8 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
                               S_028208_BR_Y(framebuffer->height));
 
        if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
+               bool disable_constant_encode =
+                       cmd_buffer->device->physical_device->has_dcc_constant_encode;
                uint8_t watermark = 4; /* Default value for GFX8. */
 
                /* For optimal DCC performance. */
@@ -1889,7 +1891,8 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
 
                radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
                                       S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
-                                      S_028424_OVERWRITE_COMBINER_WATERMARK(watermark));
+                                      S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
+                                      S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
        }
 
        if (cmd_buffer->device->dfsm_allowed) {

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 26b31cff9f14d369c5d209ebf4421a22c8772987..f12b8bde1f90fd5bf6b810635d29bea22a7268e0 100644 (file)
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -371,6 +371,8 @@ radv_physical_device_init(struct radv_physical_device *device,
                                       (device->rad_info.chip_class >= GFX8 &&
                                        device->rad_info.me_fw_feature >= 41);
 
+       device->has_dcc_constant_encode = device->rad_info.family == CHIP_RAVEN2;
+
        device->use_shader_ballot = device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT;
 
        radv_physical_device_init_mem_types(device);

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 284d212d027826ac4f387cb62e1e73d275dca969..b537778001c7c72753d5a3ff3483485ce3df506d 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -319,6 +319,9 @@ struct radv_physical_device {
        /* Whether to enable the AMD_shader_ballot extension */
        bool use_shader_ballot;
 
+       /* Whether DISABLE_CONSTANT_ENCODE_REG is supported. */
+       bool has_dcc_constant_encode;
+
        /* This is the drivers on-disk cache used as a fallback as opposed to
         * the pipeline cache defined by apps.
         */