+2018-03-01 Tom de Vries <tom@codesourcery.com>
+
+ PR rtl-optimization/83327
+ * lra-int.h (hard_regs_spilled_into): Declare.
+ * lra.c (hard_regs_spilled_into): Define.
+ (init_reg_info): Init hard_regs_spilled_into.
+ * lra-spills.c (assign_spill_hard_regs): Update hard_regs_spilled_into.
+ * lra-lives.c (make_hard_regno_born, make_hard_regno_dead)
+ (process_bb_lives): Handle hard_regs_spilled_into.
+ (lra_create_live_ranges_1): Before doing liveness propagation, clear
+ regs in all_hard_regs_bitmap if set in hard_regs_spilled_into.
+
2018-02-28 David Edelsohn <dje.gcc@gmail.com>
* config.gcc (powerpc-ibm-aix7.1.*): New stanza.
/* References to the common info about each register. */
extern struct lra_reg *lra_reg_info;
+extern HARD_REG_SET hard_regs_spilled_into;
+
/* Static info about each insn operand (common for all insns with the
same ICODE). Warning: if the structure definition is changed, the
initializer for debug_operand_data in lra.c should be changed
|| i != REGNO (pic_offset_table_rtx))
#endif
SET_HARD_REG_BIT (lra_reg_info[i].conflict_hard_regs, regno);
- if (fixed_regs[regno])
+ if (fixed_regs[regno] || TEST_HARD_REG_BIT (hard_regs_spilled_into, regno))
bitmap_set_bit (bb_gen_pseudos, regno);
}
return;
sparseset_set_bit (start_dying, regno);
CLEAR_HARD_REG_BIT (hard_regs_live, regno);
- if (fixed_regs[regno])
+ if (fixed_regs[regno] || TEST_HARD_REG_BIT (hard_regs_spilled_into, regno))
{
bitmap_clear_bit (bb_gen_pseudos, regno);
bitmap_set_bit (bb_killed_pseudos, regno);
check_pseudos_live_through_calls (j, last_call_used_reg_set);
}
+ for (i = 0; i < FIRST_PSEUDO_REGISTER; ++i)
+ {
+ if (!TEST_HARD_REG_BIT (hard_regs_live, i))
+ continue;
+
+ if (!TEST_HARD_REG_BIT (hard_regs_spilled_into, i))
+ continue;
+
+ if (bitmap_bit_p (df_get_live_in (bb), i))
+ continue;
+
+ live_change_p = true;
+ if (lra_dump_file)
+ fprintf (lra_dump_file,
+ " hard reg r%d is added to live at bb%d start\n", i,
+ bb->index);
+ bitmap_set_bit (df_get_live_in (bb), i);
+ }
+
if (need_curr_point_incr)
next_program_point (curr_point, freq);
}
/* As we did not change CFG since LRA start we can use
DF-infrastructure solver to solve live data flow problem. */
+ for (int i = 0; i < FIRST_PSEUDO_REGISTER; ++i)
+ {
+ if (TEST_HARD_REG_BIT (hard_regs_spilled_into, i))
+ bitmap_clear_bit (&all_hard_regs_bitmap, i);
+ }
df_simple_dataflow
(DF_BACKWARD, NULL, live_con_fun_0, live_con_fun_n,
live_trans_fun, &all_blocks,
}
if (lra_dump_file != NULL)
fprintf (lra_dump_file, " Spill r%d into hr%d\n", regno, hard_regno);
+ add_to_hard_reg_set (&hard_regs_spilled_into,
+ lra_reg_info[regno].biggest_mode, hard_regno);
/* Update reserved_hard_regs. */
for (r = lra_reg_info[regno].live_ranges; r != NULL; r = r->next)
for (p = r->start; p <= r->finish; p++)
/* Common info about each register. */
struct lra_reg *lra_reg_info;
+HARD_REG_SET hard_regs_spilled_into;
+
/* Last register value. */
static int last_reg_value;
for (i = 0; i < reg_info_size; i++)
initialize_lra_reg_info_element (i);
copy_vec.truncate (0);
+ CLEAR_HARD_REG_SET (hard_regs_spilled_into);
}