--- /dev/null
+import random
+from openpower.test.common import TestAccumulatorBase
+from openpower.endian import bigendian
+from openpower.simulator.program import Program
+from openpower.decoder.selectable_int import SelectableInt
+from openpower.decoder.power_enums import XER_bits
+from openpower.decoder.isa.caller import special_sprs
+import unittest
+
+
+class ALUTestCase(TestAccumulatorBase):
+
+ def case_1_regression(self):
+ lst = [f"extsw 3, 1"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0xb6a1fc6c8576af91
+ self.add_case(Program(lst, bigendian), initial_regs)
+ lst = [f"subf 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x3d7f3f7ca24bac7b
+ initial_regs[2] = 0xf6b2ac5e13ee15c2
+ self.add_case(Program(lst, bigendian), initial_regs)
+ lst = [f"subf 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x833652d96c7c0058
+ initial_regs[2] = 0x1c27ecff8a086c1a
+ self.add_case(Program(lst, bigendian), initial_regs)
+ lst = [f"extsb 3, 1"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x7f9497aaff900ea0
+ self.add_case(Program(lst, bigendian), initial_regs)
+ lst = [f"add. 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0xc523e996a8ff6215
+ initial_regs[2] = 0xe1e5b9cc9864c4a8
+ self.add_case(Program(lst, bigendian), initial_regs)
+ lst = [f"add 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x2e08ae202742baf8
+ initial_regs[2] = 0x86c43ece9efe5baa
+ self.add_case(Program(lst, bigendian), initial_regs)
+
+ def case_rand(self):
+ insns = ["add", "add.", "subf"]
+ for i in range(40):
+ choice = random.choice(insns)
+ lst = [f"{choice} 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = random.randint(0, (1 << 64)-1)
+ initial_regs[2] = random.randint(0, (1 << 64)-1)
+ self.add_case(Program(lst, bigendian), initial_regs)
+
+ def case_addme_ca_0(self):
+ insns = ["addme", "addme.", "addmeo", "addmeo."]
+ for choice in insns:
+ lst = [f"{choice} 6, 16"]
+ for value in [0x7ffffffff,
+ 0xffff80000]:
+ initial_regs = [0] * 32
+ initial_regs[16] = value
+ initial_sprs = {}
+ xer = SelectableInt(0, 64)
+ xer[XER_bits['CA']] = 0
+ initial_sprs[special_sprs['XER']] = xer
+ self.add_case(Program(lst, bigendian),
+ initial_regs, initial_sprs)
+
+ def case_addme_ca_1(self):
+ insns = ["addme", "addme.", "addmeo", "addmeo."]
+ for choice in insns:
+ lst = [f"{choice} 6, 16"]
+ for value in [0x7ffffffff, # fails, bug #476
+ 0xffff80000]:
+ initial_regs = [0] * 32
+ initial_regs[16] = value
+ initial_sprs = {}
+ xer = SelectableInt(0, 64)
+ xer[XER_bits['CA']] = 1
+ initial_sprs[special_sprs['XER']] = xer
+ self.add_case(Program(lst, bigendian),
+ initial_regs, initial_sprs)
+
+ def case_addme_ca_so_3(self):
+ """bug where SO does not get passed through to CR0
+ """
+ lst = ["addme. 6, 16"]
+ initial_regs = [0] * 32
+ initial_regs[16] = 0x7ffffffff
+ initial_sprs = {}
+ xer = SelectableInt(0, 64)
+ xer[XER_bits['CA']] = 1
+ xer[XER_bits['SO']] = 1
+ initial_sprs[special_sprs['XER']] = xer
+ self.add_case(Program(lst, bigendian),
+ initial_regs, initial_sprs)
+
+ def case_addze(self):
+ insns = ["addze", "addze.", "addzeo", "addzeo."]
+ for choice in insns:
+ lst = [f"{choice} 6, 16"]
+ initial_regs = [0] * 32
+ initial_regs[16] = 0x00ff00ff00ff0080
+ self.add_case(Program(lst, bigendian), initial_regs)
+
+ self.add_case(Program(lst, bigendian), initial_regs)
+
+ def case_addis_nonzero_r0_regression(self):
+ lst = [f"addis 3, 0, 1"]
+ print(lst)
+ initial_regs = [0] * 32
+ initial_regs[0] = 5
+ self.add_case(Program(lst, bigendian), initial_regs)
+
+ def case_addis_nonzero_r0(self):
+ for i in range(10):
+ imm = random.randint(-(1 << 15), (1 << 15)-1)
+ lst = [f"addis 3, 0, {imm}"]
+ print(lst)
+ initial_regs = [0] * 32
+ initial_regs[0] = random.randint(0, (1 << 64)-1)
+ self.add_case(Program(lst, bigendian), initial_regs)
+
+ def case_rand_imm(self):
+ insns = ["addi", "addis", "subfic"]
+ for i in range(10):
+ choice = random.choice(insns)
+ imm = random.randint(-(1 << 15), (1 << 15)-1)
+ lst = [f"{choice} 3, 1, {imm}"]
+ print(lst)
+ initial_regs = [0] * 32
+ initial_regs[1] = random.randint(0, (1 << 64)-1)
+ self.add_case(Program(lst, bigendian), initial_regs)
+
+ def case_0_adde(self):
+ lst = ["adde. 5, 6, 7"]
+ for i in range(10):
+ initial_regs = [0] * 32
+ initial_regs[6] = random.randint(0, (1 << 64)-1)
+ initial_regs[7] = random.randint(0, (1 << 64)-1)
+ initial_sprs = {}
+ xer = SelectableInt(0, 64)
+ xer[XER_bits['CA']] = 1
+ initial_sprs[special_sprs['XER']] = xer
+ self.add_case(Program(lst, bigendian),
+ initial_regs, initial_sprs)
+
+ def case_cmp(self):
+ lst = ["subf. 1, 6, 7",
+ "cmp cr2, 1, 6, 7"]
+ initial_regs = [0] * 32
+ initial_regs[6] = 0x10
+ initial_regs[7] = 0x05
+ self.add_case(Program(lst, bigendian), initial_regs, {})
+
+ def case_cmp2(self):
+ lst = ["cmp cr2, 0, 2, 3"]
+ initial_regs = [0] * 32
+ initial_regs[2] = 0xffffffffaaaaaaaa
+ initial_regs[3] = 0x00000000aaaaaaaa
+ self.add_case(Program(lst, bigendian), initial_regs, {})
+
+ lst = ["cmp cr2, 0, 4, 5"]
+ initial_regs = [0] * 32
+ initial_regs[4] = 0x00000000aaaaaaaa
+ initial_regs[5] = 0xffffffffaaaaaaaa
+ self.add_case(Program(lst, bigendian), initial_regs, {})
+
+ def case_cmp3(self):
+ lst = ["cmp cr2, 1, 2, 3"]
+ initial_regs = [0] * 32
+ initial_regs[2] = 0xffffffffaaaaaaaa
+ initial_regs[3] = 0x00000000aaaaaaaa
+ self.add_case(Program(lst, bigendian), initial_regs, {})
+
+ lst = ["cmp cr2, 1, 4, 5"]
+ initial_regs = [0] * 32
+ initial_regs[4] = 0x00000000aaaaaaaa
+ initial_regs[5] = 0xffffffffaaaaaaaa
+ self.add_case(Program(lst, bigendian), initial_regs, {})
+
+ def case_cmpl_microwatt_0(self):
+ """microwatt 1.bin:
+ 115b8: 40 50 d1 7c .long 0x7cd15040 # cmpl 6, 0, 17, 10
+ register_file.vhdl: Reading GPR 11 000000000001C026
+ register_file.vhdl: Reading GPR 0A FEDF3FFF0001C025
+ cr_file.vhdl: Reading CR 35055050
+ cr_file.vhdl: Writing 35055058 to CR mask 01 35055058
+ """
+
+ lst = ["cmpl 6, 0, 17, 10"]
+ initial_regs = [0] * 32
+ initial_regs[0x11] = 0x1c026
+ initial_regs[0xa] = 0xFEDF3FFF0001C025
+ XER = 0xe00c0000
+ CR = 0x35055050
+
+ self.add_case(Program(lst, bigendian), initial_regs,
+ initial_sprs = {'XER': XER},
+ initial_cr = CR)
+
+ def case_cmpl_microwatt_0_disasm(self):
+ """microwatt 1.bin: disassembled version
+ 115b8: 40 50 d1 7c .long 0x7cd15040 # cmpl 6, 0, 17, 10
+ register_file.vhdl: Reading GPR 11 000000000001C026
+ register_file.vhdl: Reading GPR 0A FEDF3FFF0001C025
+ cr_file.vhdl: Reading CR 35055050
+ cr_file.vhdl: Writing 35055058 to CR mask 01 35055058
+ """
+
+ dis = ["cmpl 6, 0, 17, 10"]
+ lst = bytes([0x40, 0x50, 0xd1, 0x7c]) # 0x7cd15040
+ initial_regs = [0] * 32
+ initial_regs[0x11] = 0x1c026
+ initial_regs[0xa] = 0xFEDF3FFF0001C025
+ XER = 0xe00c0000
+ CR = 0x35055050
+
+ p = Program(lst, bigendian)
+ p.assembly = '\n'.join(dis)+'\n'
+ self.add_case(p, initial_regs,
+ initial_sprs = {'XER': XER},
+ initial_cr = CR)
+
+ def case_cmplw_microwatt_1(self):
+ """microwatt 1.bin:
+ 10d94: 40 20 96 7c cmplw cr1,r22,r4
+ gpr: 00000000ffff6dc1 <- r4
+ gpr: 0000000000000000 <- r22
+ """
+
+ lst = ["cmpl 1, 0, 22, 4"]
+ initial_regs = [0] * 32
+ initial_regs[4] = 0xffff6dc1
+ initial_regs[22] = 0
+ XER = 0xe00c0000
+ CR = 0x50759999
+
+ self.add_case(Program(lst, bigendian), initial_regs,
+ initial_sprs = {'XER': XER},
+ initial_cr = CR)
+
+ def case_cmpli_microwatt(self):
+ """microwatt 1.bin: cmpli
+ 123ac: 9c 79 8d 2a cmpli cr5,0,r13,31132
+ gpr: 00000000301fc7a7 <- r13
+ cr : 0000000090215393
+ xer: so 1 ca 0 32 0 ov 0 32 0
+
+ """
+
+ lst = ["cmpli 5, 0, 13, 31132"]
+ initial_regs = [0] * 32
+ initial_regs[13] = 0x301fc7a7
+ XER = 0xe00c0000
+ CR = 0x90215393
+
+ self.add_case(Program(lst, bigendian), initial_regs,
+ initial_sprs = {'XER': XER},
+ initial_cr = CR)
+
+ def case_extsb(self):
+ insns = ["extsb", "extsh", "extsw"]
+ for i in range(10):
+ choice = random.choice(insns)
+ lst = [f"{choice} 3, 1"]
+ print(lst)
+ initial_regs = [0] * 32
+ initial_regs[1] = random.randint(0, (1 << 64)-1)
+ self.add_case(Program(lst, bigendian), initial_regs)
+
+ def case_cmpeqb(self):
+ lst = ["cmpeqb cr1, 1, 2"]
+ for i in range(20):
+ initial_regs = [0] * 32
+ initial_regs[1] = i
+ initial_regs[2] = 0x0001030507090b0f
+ self.add_case(Program(lst, bigendian), initial_regs, {})
+
--- /dev/null
+import random
+import unittest
+from openpower.simulator.program import Program
+from openpower.endian import bigendian
+from openpower.test.common import TestAccumulatorBase, skip_case
+
+from openpower.util import log_rand
+
+
+class DivTestCases(TestAccumulatorBase):
+ def case_divdeu_regression(self):
+ lst = ["divdeu 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x1
+ initial_regs[2] = 0x2
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_divde_regression3(self):
+ lst = ["divde 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x8000000000000000
+ initial_regs[2] = 0xFFFFFFFFFFFFFFFF
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_divwe_regression2(self):
+ lst = ["divwe 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x80000000
+ initial_regs[2] = 0xFFFFFFFF
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_divde_regression2(self):
+ lst = ["divde 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x1
+ initial_regs[2] = 0xfffffffffffffffe
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_divde_regression(self):
+ lst = ["divde 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[2] = 0x1
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_moduw_regression(self):
+ lst = ["moduw 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x1
+ initial_regs[2] = 0xffffffffffffffff
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_modsw_regression(self):
+ lst = ["modsw 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0xffffffffffffffff
+ initial_regs[2] = 0x2
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_divweu_regression(self):
+ # simulator is wrong, FSM and power-instruction-analyzer both correct
+ lst = ["divweu 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x1
+ initial_regs[2] = 0xffffffffffffffff
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_divwe_regression(self):
+ # div FU and power-instruction-analyzer both correctly return 0
+ # hitting behavior undefined by Power v3.1 spec, need to adjust
+ # simulator API to tell tests that the simulator's output doesn't
+ # need to completely match
+ lst = [f"divwe 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 1
+ initial_regs[2] = 1
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_divwe__regression(self):
+ lst = ["divwe. 3, 1, 2"]
+ initial_regs = [0] * 32
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_divw_regression(self):
+ # simulator is wrong, FSM and power-instruction-analyzer both correct
+ lst = [f"divw 0, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[2] = 0x2
+ initial_regs[1] = 0x80000000
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ # modulo
+ def case_modsd_regression2(self):
+ lst = [f"modsd 0, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[2] = 0xff
+ initial_regs[1] = 0x7fffffffffffffff
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ # modulo
+ def case_modsd_regression(self):
+ lst = [f"modsd 17, 27, 0"]
+ initial_regs = [0] * 32
+ initial_regs[0] = 0xff
+ initial_regs[27] = 0x7fffffffffffffff
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_divduo_regression(self):
+ lst = [f"divduo. 11, 20, 6"]
+ initial_regs = [0] * 32
+ # gpr: 00ff00ff00ff0080 <- r6
+ # gpr: 000000000000007f <- r11
+ # gpr: 7f6e5d4c3b2a1908 <- r20
+ initial_regs[6] = 0x00ff00ff00ff0080
+ initial_regs[20] = 0x7f6e5d4c3b2a1908
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_0_regression(self):
+ for i in range(40):
+ lst = ["divwo 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0xbc716835f32ac00c
+ initial_regs[2] = 0xcdf69a7f7042db66
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_1_regression(self):
+ lst = ["divwo 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x10000000000000000-4
+ initial_regs[2] = 0x10000000000000000-2
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_2_regression(self):
+ lst = ["divwo 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0xffffffffffff9321
+ initial_regs[2] = 0xffffffffffff7012
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_3_regression(self):
+ lst = ["divwo. 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x1b8e32f2458746af
+ initial_regs[2] = 0x6b8aee2ccf7d62e9
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_4_regression(self):
+ lst = ["divw 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x1c4e6c2f3aa4a05c
+ initial_regs[2] = 0xe730c2eed6cc8dd7
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_5_regression(self):
+ lst = ["divw 3, 1, 2",
+ "divwo. 6, 4, 5"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x1c4e6c2f3aa4a05c
+ initial_regs[2] = 0xe730c2eed6cc8dd7
+ initial_regs[4] = 0x1b8e32f2458746af
+ initial_regs[5] = 0x6b8aee2ccf7d62e9
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_6_regression(self):
+ # CR0 not getting set properly for this one
+ # turns out that overflow is not set correctly in
+ # fu/div/output_stage.py calc_overflow
+ # https://bugs.libre-soc.org/show_bug.cgi?id=425
+ lst = ["divw. 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x61c1cc3b80f2a6af
+ initial_regs[2] = 0x9dc66a7622c32bc0
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_7_regression(self):
+ # https://bugs.libre-soc.org/show_bug.cgi?id=425
+ lst = ["divw. 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0xf1791627e05e8096
+ initial_regs[2] = 0xffc868bf4573da0b
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_8_fsm_regression(self): # FSM result is "36" not 6
+ lst = ["divwu. 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 18
+ initial_regs[2] = 3
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_9_regression(self): # CR0 fails: expected 0b10, actual 0b11
+ lst = ["divw. 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 1
+ initial_regs[2] = 0
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_10_regression(self): # overflow fails
+ lst = ["divwo 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0xbc716835f32ac00c
+ initial_regs[2] = 0xcdf69a7f7042db66
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_11_regression(self):
+ lst = ["divwo. 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0xffffffffffffffff
+ initial_regs[2] = 0xffffffffffffffff
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_divw_by_zero_1(self):
+ lst = ["divw. 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x1
+ initial_regs[2] = 0x0
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_divw_overflow2(self):
+ lst = ["divw. 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x80000000
+ initial_regs[2] = 0xffffffffffffffff # top bits don't seem to matter
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_divw_overflow3(self):
+ lst = ["divw. 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x80000000
+ initial_regs[2] = 0xffffffff
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_divwuo_regression_1(self):
+ lst = ["divwuo. 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x7591a398c4e32b68
+ initial_regs[2] = 0x48674ab432867d69
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_divwuo_1(self):
+ lst = ["divwuo. 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x50
+ initial_regs[2] = 0x2
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_rand_divwu(self):
+ insns = ["divwu", "divwu.", "divwuo", "divwuo."]
+ for i in range(40):
+ choice = random.choice(insns)
+ lst = [f"{choice} 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = log_rand(32)
+ initial_regs[2] = log_rand(32)
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
+ def case_rand_divw(self):
+ insns = ["divw", "divw.", "divwo", "divwo."]
+ for i in range(40):
+ choice = random.choice(insns)
+ lst = [f"{choice} 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = log_rand(32)
+ initial_regs[2] = log_rand(32)
+ with Program(lst, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
--- /dev/null
+from openpower.simulator.program import Program
+from openpower.endian import bigendian
+
+from openpower.test.common import TestAccumulatorBase
+
+
+class DivTestLong(TestAccumulatorBase):
+ def case_all(self):
+ instrs = []
+ for width in ("w", "d"):
+ for sign in ("", "u"):
+ for ov in ("", "o"):
+ for cnd in ("", "."):
+ instrs += ["div" + width + sign + ov + cnd,
+ "div" + width + "e" + sign + ov + cnd]
+ for sign in ("s", "u"):
+ instrs += ["mod" + sign + width]
+ test_values = [
+ 0x0,
+ 0x1,
+ 0x2,
+ 0xFFFF_FFFF_FFFF_FFFF,
+ 0xFFFF_FFFF_FFFF_FFFE,
+ 0x7FFF_FFFF_FFFF_FFFF,
+ 0x8000_0000_0000_0000,
+ 0x1234_5678_0000_0000,
+ 0x1234_5678_8000_0000,
+ 0x1234_5678_FFFF_FFFF,
+ 0x1234_5678_7FFF_FFFF,
+ ]
+ for instr in instrs:
+ l = [f"{instr} 3, 1, 2"]
+ for ra in test_values:
+ for rb in test_values:
+ initial_regs = [0] * 32
+ initial_regs[1] = ra
+ initial_regs[2] = rb
+ # use "with" so as to close the files used
+ with Program(l, bigendian) as prog:
+ self.add_case(prog, initial_regs)
+
--- /dev/null
+from openpower.simulator.program import Program
+from openpower.endian import bigendian
+from openpower.consts import MSR
+
+
+from openpower.test.common import TestAccumulatorBase, skip_case
+import random
+
+
+#incomplete test - connect fsm inputs first
+class MMUTestCase(TestAccumulatorBase):
+ # MMU handles MTSPR, MFSPR, DCBZ and TLBIE.
+ # other instructions here -> must be load/store
+
+ #before running the test case: set DISR and DAR
+
+ def case_mfspr_after_invalid_load(self):
+ lst = [ # TODO -- set SPR on both simulator and port interface
+ "mfspr 1, 18", # DSISR to reg 1
+ "mfspr 2, 19", # DAR to reg 2
+ # TODO -- verify returned sprvals
+ ]
+
+ initial_regs = [0] * 32
+
+ initial_sprs = {'DSISR': 0x12345678, 'DAR': 0x87654321}
+ self.add_case(Program(lst, bigendian),
+ initial_regs, initial_sprs)
+
+import random
from openpower.consts import FastRegsEnum
from openpower.decoder.power_enums import SPRfull as SPR, spr_dict
return res
+# makes a logarithmically-skewed random number
+def log_rand(n, min_val=1):
+ logrange = random.randint(1, n)
+ return random.randint(min_val, (1 << logrange)-1)
projects / openpower-isa.git / commitdiff