gensdrphy: fix memtype and change phase shift in comments.

diff --git a/misoclib/sdramphy/gensdrphy.py b/misoclib/sdramphy/gensdrphy.py
index fbb5bd4eb8ac390c158efc1b5a37f145e7a208e0..450e456e7ec85c3233da80aba7a0f9ee168fcab0 100644 (file)
--- a/misoclib/sdramphy/gensdrphy.py
+++ b/misoclib/sdramphy/gensdrphy.py
@@ -7,7 +7,7 @@
 # The PHY needs 2 Clock domains:
 #  - sys_clk    : The System Clock domain
 #  - sys_clk_ps : The System Clock domain with its phase shifted 
-#                 (-0.75ns on C4@100MHz)
+#                 (-3ns on C4@100MHz)
 #
 # Assert dfi_wrdata_en and present the data 
 # on dfi_wrdata_mask/dfi_wrdata in the same
@@ -35,7 +35,7 @@ class GENSDRPHY(Module):
                d = flen(pads.dq)
 
                self.phy_settings = lasmicon.PhySettings(
-                       memtype=memtype,
+                       memtype="SDR",
                        dfi_d=d,
                        nphases=1,
                        rdphase=0,