changes in verilog frontend for new $mem/$memwr WR_EN interface

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 787f4d2d8cb505aab111e2813397bbfcf1466cd6..a2fdcf8b1d3d4e4427255a0eb3a77630c03489b3 100644 (file)
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1287,9 +1287,6 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
                        cell->connections["\\DATA"] = children[1]->genWidthRTLIL(current_module->memories[str]->width);
                        cell->connections["\\EN"] = children[2]->genRTLIL();
 
-                       if (cell->connections["\\EN"].width > 1)
-                               cell->connections["\\EN"] = uniop2rtlil(this, "$reduce_bool", 1, cell->connections["\\EN"], false);
-
                        cell->parameters["\\MEMID"] = RTLIL::Const(str);
                        cell->parameters["\\ABITS"] = RTLIL::Const(addr_bits);
                        cell->parameters["\\WIDTH"] = RTLIL::Const(current_module->memories[str]->width);

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index e547ede36f85a7e1c8eced5fa7f2d4097589b682..ba0dca139756a760705426f10f70820b7f3569b6 100644 (file)
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1177,17 +1177,19 @@ skip_dynamic_range_lvalue_expansion:;
                current_scope[wire_data->str] = wire_data;
                while (wire_data->simplify(true, false, false, 1, -1, false, false)) { }
 
-               AstNode *wire_en = new AstNode(AST_WIRE);
+               AstNode *wire_en = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true)));
                wire_en->str = id_en;
                current_ast_mod->children.push_back(wire_en);
                current_scope[wire_en->str] = wire_en;
                while (wire_en->simplify(true, false, false, 1, -1, false, false)) { }
 
-               std::vector<RTLIL::State> x_bits_addr, x_bits_data;
+               std::vector<RTLIL::State> x_bits_addr, x_bits_data, set_bits_en;
                for (int i = 0; i < addr_bits; i++)
                        x_bits_addr.push_back(RTLIL::State::Sx);
                for (int i = 0; i < mem_width; i++)
                        x_bits_data.push_back(RTLIL::State::Sx);
+               for (int i = 0; i < mem_width; i++)
+                       set_bits_en.push_back(RTLIL::State::S1);
 
                AstNode *assign_addr = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bits_addr, false));
                assign_addr->children[0]->str = id_addr;
@@ -1195,7 +1197,7 @@ skip_dynamic_range_lvalue_expansion:;
                AstNode *assign_data = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bits_data, false));
                assign_data->children[0]->str = id_data;
 
-               AstNode *assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_int(0, false, 1));
+               AstNode *assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_int(0, false, mem_width));
                assign_en->children[0]->str = id_en;
 
                AstNode *default_signals = new AstNode(AST_BLOCK);
@@ -1210,7 +1212,7 @@ skip_dynamic_range_lvalue_expansion:;
                assign_data = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), children[1]->clone());
                assign_data->children[0]->str = id_data;
 
-               assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_int(1, false, 1));
+               assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(set_bits_en, false));
                assign_en->children[0]->str = id_en;
 
                newNode = new AstNode(AST_BLOCK);