use new submodules/specials/clock_domains automatic collection

diff --git a/miscope/mila.py b/miscope/mila.py
index abf8e79c9e63555624b193bd1ae31c8c96664c0a..fe0c014297549399d5cf79dd40c0079aa11e4a55 100644 (file)
--- a/miscope/mila.py
+++ b/miscope/mila.py
@@ -67,15 +67,15 @@ class MiLa(Module, AutoCSR):
                                sink.dat.eq(dat)
                        ]
 
-               self.submodules.trigger = trigger = Trigger(self.width, self.ports)
-               self.submodules.recorder = recorder = Recorder(self.width, self.depth)
+               self.trigger = trigger = Trigger(self.width, self.ports)
+               self.recorder = recorder = Recorder(self.width, self.depth)
                self.comb += [
                        sink.connect(trigger.sink),
                        trigger.source.connect(recorder.trig_sink)
                ]
 
                if self.with_rle:
-                       self.submodules.rle = rle = RunLengthEncoder(self.width)
+                       self.rle = rle = RunLengthEncoder(self.width)
                        self.comb += [
                                sink.connect(rle.sink),
                                rle.source.connect(recorder.dat_sink)

diff --git a/miscope/trigger.py b/miscope/trigger.py
index 6e795f52fc27924973e743d16baf0e1e034b755a..d27fa65ca487e50ea081273833908dcda95a8173 100644 (file)
--- a/miscope/trigger.py
+++ b/miscope/trigger.py
@@ -124,9 +124,9 @@ class Trigger(Module, AutoCSR):
                self.width = width
                self.ports = ports
 
-               self.submodules.sum = Sum(len(ports))
+               self.sum = Sum(len(ports))
                for i, port in enumerate(ports):
-                       setattr(self.submodules, "port"+str(i), port)
+                       setattr(self, "port"+str(i), port)
 
                self.sink   = Record(dat_layout(width))
                self.source = self.sum.source

diff --git a/miscope/uart2wishbone.py b/miscope/uart2wishbone.py
index b697f51f1264f6689956dc8f67d106880e47df08..6b5c0cf7b679f8ab50fc927bea8876ebe753eea1 100644 (file)
--- a/miscope/uart2wishbone.py
+++ b/miscope/uart2wishbone.py
@@ -14,8 +14,8 @@ class UART(Module, AutoCSR):
 
                ###
 
-               self.submodules.rx = UARTRX(pads, tuning_word)
-               self.submodules.tx = UARTTX(pads, tuning_word)
+               self.rx = UARTRX(pads, tuning_word)
+               self.tx = UARTTX(pads, tuning_word)
 
 class Counter(Module):
        def __init__(self, width):
@@ -75,12 +75,12 @@ class UART2Wishbone(Module, AutoCSR):
 
        ###
                if share_uart:
-                       self.submodules.uart_mux = UARTMux(pads)
-                       self.submodules.uart = UART(self.uart_mux.bridge_pads, clk_freq, baud)
+                       self.uart_mux = UARTMux(pads)
+                       self.uart = UART(self.uart_mux.bridge_pads, clk_freq, baud)
                        self.shared_pads = self.uart_mux.shared_pads
                        self.comb += self.uart_mux.sel.eq(self._sel.storage)
                else:
-                       self.submodules.uart = UART(pads, clk_freq, baud)
+                       self.uart = UART(pads, clk_freq, baud)
 
                uart = self.uart
 

diff --git a/sim/tb_recorder_csr.py b/sim/tb_recorder_csr.py
index c17cbb74864d5f6686569c212c5015a667fe6a35..5a882fa88e0a3913e87784045bfb8c95408c0f4e 100644 (file)
--- a/sim/tb_recorder_csr.py
+++ b/sim/tb_recorder_csr.py
@@ -40,7 +40,7 @@ def csr_configure(bus, regs):
 
        # Offset
        regs.recorder_offset.write(0)
-       
+
        # Trigger
        regs.recorder_trigger.write(1)
 
@@ -58,7 +58,7 @@ def csr_transactions(bus, regs):
 
        for t in range(100):
                yield None
-       
+
        global triggered
        triggered = True
 
@@ -81,10 +81,10 @@ class TB(Module):
                self.csr_base = 0
 
                # Recorder
-               self.submodules.recorder = Recorder(32, 1024)
-       
+               self.recorder = Recorder(32, 1024)
+
                # Csr
-               self.submodules.csrbankarray = csrgen.BankArray(self, 
+               self.csrbankarray = csrgen.BankArray(self,
                        lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])
 
                # Csr Master
@@ -93,16 +93,16 @@ class TB(Module):
 
                bus = Csr2Trans()
                regs = build_map(addrmap, bus.read_csr, bus.write_csr)
-               self.submodules.master = csr.Initiator(csr_transactions(bus, regs))
+               self.master = csr.Initiator(csr_transactions(bus, regs))
 
-               self.submodules.csrcon = csr.Interconnect(self.master.bus,      self.csrbankarray.get_buses())
+               self.csrcon = csr.Interconnect(self.master.bus, self.csrbankarray.get_buses())
 
        # Recorder Data
        def recorder_data(self, selfp):
                selfp.recorder.dat_sink.stb = 1
                if not hasattr(self, "cnt"):
                        self.cnt = 0
-               self.cnt += 1   
+               self.cnt += 1
 
                selfp.recorder.dat_sink.dat =  self.cnt
 

diff --git a/sim/tb_rle.py b/sim/tb_rle.py
index 9ce98a46ce41ae3a1e6b23c2a6880b162e011a37..68ccf0dff184d775f0ffd5233f74176a731af564 100644 (file)
--- a/sim/tb_rle.py
+++ b/sim/tb_rle.py
@@ -24,9 +24,9 @@ rle_test_seq = iter(
 
 class TB(Module):
        def __init__(self):
-               
+
                # Rle
-               self.submodules.rle = storage.RunLengthEncoder(16, 32)
+               self.rle = storage.RunLengthEncoder(16, 32)
 
        def do_simulation(self, selfp):
                selfp.rle._r_enable.storage = 1

diff --git a/sim/tb_trigger_csr.py b/sim/tb_trigger_csr.py
index bc796ed84ad8164d3790cbf50958d78797023845..66390a4456d55ea78916f026e39cca4ea4328995 100644 (file)
--- a/sim/tb_trigger_csr.py
+++ b/sim/tb_trigger_csr.py
@@ -22,7 +22,7 @@ class Csr2Trans():
 
        def read_csr(self, adr):
                self.t.append(TRead(adr//4))
-       
+
 def csr_prog_mila(bus, regs):
        regs.trigger_port0_mask.write(0xFFFFFFFF)
        regs.trigger_port0_trig.write(0xDEADBEEF)
@@ -60,27 +60,27 @@ class TB(Module):
        }
        def __init__(self, addrmap=None):
                self.csr_base = 0
-                       
+
                # Trigger
                term0 = Term(32)
                term1 = Term(32)
                term2 = Term(32)
                term3 = Term(32)
-               self.submodules.trigger = Trigger(32, [term0, term1, term2, term3])
-       
+               self.trigger = Trigger(32, [term0, term1, term2, term3])
+
                # Csr
-               self.submodules.csrbankarray = csrgen.BankArray(self, 
+               self.csrbankarray = csrgen.BankArray(self,
                        lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])
-               
+
                # Csr Master
                csr_header = get_csr_csv(self.csr_base, self.csrbankarray)
                write_to_file("csr.csv", csr_header)
-               
+
                bus = Csr2Trans()
                regs = build_map(addrmap, bus.read_csr, bus.write_csr)
-               self.submodules.master = csr.Initiator(csr_transactions(bus, regs))
-               
-               self.submodules.csrcon = csr.Interconnect(self.master.bus,      self.csrbankarray.get_buses())
+               self.master = csr.Initiator(csr_transactions(bus, regs))
+
+               self.csrcon = csr.Interconnect(self.master.bus, self.csrbankarray.get_buses())
 
                self.terms = [term0, term1, term2, term3]