Capture all data in one "abc_flop" attribute

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index 9f6f9c47ea4413f5c0fc53cfb9734ded71bb9985..a9172026097ca8b4b88669d039591c17ccc28fd3 100644 (file)
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -23,7 +23,7 @@
 module \$__ABC_FF_ (input C, D, output Q);
 endmodule
 
-(* abc_box_id = 7, lib_whitebox, abc_flop = "FDRE", abc_flop_q = "Q", abc_flop_d = "D", abc_flop_past_q = "\\$pastQ" *)
+(* abc_box_id = 7, lib_whitebox, abc_flop = "FDRE,D,Q,\\$pastQ" *)
 module \$__ABC_FDRE (output Q, input C, CE, D, R, \$pastQ );
   parameter [0:0] INIT = 1'b0;
   //parameter [0:0] IS_C_INVERTED = 1'b0;