next = new_block();
next->start = (fs_inst *)inst->next;
- if (inst->predicated)
+ if (inst->predicate)
cur->add_successor(mem_ctx, next);
set_next_block(next);
next = new_block();
next->start = (fs_inst *)inst->next;
- if (inst->predicated)
+ if (inst->predicate)
cur->add_successor(mem_ctx, next);
set_next_block(next);
src[1].equals(inst->src[1]) &&
src[2].equals(inst->src[2]) &&
saturate == inst->saturate &&
- predicated == inst->predicated &&
+ predicate == inst->predicate &&
conditional_mod == inst->conditional_mod &&
mlen == inst->mlen &&
base_mrf == inst->base_mrf &&
emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS, attr);
fs_inst *inst = emit_linterp(attr, fs_reg(interp),
interpolation_mode, false);
- inst->predicated = true;
+ inst->predicate = BRW_PREDICATE_NORMAL;
inst->predicate_inverse = true;
}
if (intel->gen < 6) {
fs_inst *inst = (fs_inst *)node;
if (inst->opcode != BRW_OPCODE_MOV ||
- inst->predicated ||
+ inst->predicate ||
inst->saturate ||
inst->src[0].file != GRF ||
inst->src[0].negate ||
continue;
if (inst->opcode != BRW_OPCODE_MOV ||
- inst->predicated ||
+ inst->predicate ||
inst->saturate ||
inst->dst.file != GRF || (inst->src[0].file != GRF &&
inst->src[0].file != UNIFORM)||
next_ip++;
if (inst->opcode != BRW_OPCODE_MOV ||
- inst->predicated ||
+ inst->predicate ||
inst->dst.file != MRF || inst->src[0].file != GRF ||
inst->dst.type != inst->src[0].type ||
inst->src[0].abs || inst->src[0].negate || inst->src[0].smear != -1)
* that writes that reg, but it would require smarter
* tracking to delay the rewriting until complete success.
*/
- if (scan_inst->predicated)
+ if (scan_inst->predicate)
break;
/* If it's half of register setup and not the same half as
if (inst->opcode == BRW_OPCODE_MOV &&
inst->dst.file == MRF &&
inst->src[0].file == GRF &&
- !inst->predicated) {
+ !inst->predicate) {
last_mrf_move[inst->dst.reg] = inst;
}
}
fs_reg reg)
{
if (end == start ||
- end->predicated ||
+ end->predicate ||
end->force_uncompressed ||
end->force_sechalf ||
!reg.equals(end->dst)) {
fs_reg dst;
fs_reg src[3];
bool saturate;
- bool predicated;
- bool predicate_inverse;
int conditional_mod; /**< BRW_CONDITIONAL_* */
int mlen; /**< SEND message length */
inst->src[0].file == IMM) &&
inst->src[0].type == inst->dst.type &&
!inst->saturate &&
- !inst->predicated &&
+ !inst->predicate &&
!inst->force_uncompressed &&
!inst->force_sechalf &&
inst->src[0].smear == -1) {
inst = (fs_inst *) inst->next) {
/* Skip some cases. */
- if (is_expression(inst) && !inst->predicated && inst->mlen == 0 &&
+ if (is_expression(inst) && !inst->predicate && inst->mlen == 0 &&
!inst->force_uncompressed && !inst->force_sechalf &&
!inst->conditional_mod)
{
dst = brw_reg_from_fs_reg(&inst->dst);
brw_set_conditionalmod(p, inst->conditional_mod);
- brw_set_predicate_control(p, inst->predicated);
+ brw_set_predicate_control(p, inst->predicate);
brw_set_predicate_inverse(p, inst->predicate_inverse);
brw_set_saturate(p, inst->saturate);
inst->conditional_mod = conditional_mod;
inst = emit(BRW_OPCODE_SEL, regoffset(dst, i), one, fs_reg(0.0f));
- inst->predicated = true;
+ inst->predicate = BRW_PREDICATE_NORMAL;
}
}
}
inst = emit(BRW_OPCODE_SEL, regoffset(dst, i),
regoffset(src[1], i), regoffset(src[2], i));
- inst->predicated = true;
+ inst->predicate = BRW_PREDICATE_NORMAL;
}
}
break;
inst->conditional_mod = BRW_CONDITIONAL_L;
inst = emit(BRW_OPCODE_IF);
- inst->predicated = true;
+ inst->predicate = BRW_PREDICATE_NORMAL;
emit(FS_OPCODE_DISCARD);
emit(BRW_OPCODE_ENDIF);
}
if (fpi->DstReg.WriteMask & WRITEMASK_Y) {
emit(BRW_OPCODE_MOV, regoffset(dst, 1), regoffset(src[0], 0));
inst = emit(BRW_OPCODE_MOV, regoffset(dst, 1), fs_reg(0.0f));
- inst->predicated = true;
+ inst->predicate = BRW_PREDICATE_NORMAL;
}
if (fpi->DstReg.WriteMask & WRITEMASK_Z) {
regoffset(src[0], 1), regoffset(src[0], 3));
inst = emit(BRW_OPCODE_MOV, regoffset(dst, 2), fs_reg(0.0f));
- inst->predicated = true;
+ inst->predicate = BRW_PREDICATE_NORMAL;
}
}
*/
if (inst->dst.file == GRF &&
inst->regs_written() == v->virtual_grf_sizes[inst->dst.reg] &&
- !inst->predicated &&
+ !inst->predicate &&
!inst->force_uncompressed &&
!inst->force_sechalf) {
int reg = inst->dst.reg;
* inst->regs_written(), then we need to unspill the destination
* since we write back out all of the regs_written().
*/
- if (inst->predicated || inst->force_uncompressed || inst->force_sechalf) {
+ if (inst->predicate || inst->force_uncompressed || inst->force_sechalf) {
fs_reg unspill_reg = inst->dst;
for (int chan = 0; chan < inst->regs_written(); chan++) {
emit_unspill(inst, unspill_reg,
add_dep(last_mrf_write[inst->base_mrf + i], n);
}
- if (inst->predicated) {
+ if (inst->predicate) {
assert(last_conditional_mod);
add_dep(last_conditional_mod, n);
}
add_dep(n, last_mrf_write[inst->base_mrf + i], 2);
}
- if (inst->predicated) {
+ if (inst->predicate) {
add_dep(n, last_conditional_mod);
}
inst->conditional_mod = conditionalmod;
inst = emit(BRW_OPCODE_SEL, dst, src0, src1);
- inst->predicated = true;
+ inst->predicate = BRW_PREDICATE_NORMAL;
}
}
inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f));
inst->conditional_mod = BRW_CONDITIONAL_G;
inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(1.0f));
- inst->predicated = true;
+ inst->predicate = BRW_PREDICATE_NORMAL;
inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f));
inst->conditional_mod = BRW_CONDITIONAL_L;
inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f));
- inst->predicated = true;
+ inst->predicate = BRW_PREDICATE_NORMAL;
break;
case ir_unop_rcp:
if (predicated || !l.equals(r)) {
fs_inst *inst = emit(BRW_OPCODE_MOV, l, r);
- inst->predicated = predicated;
+ inst->predicate = predicated ? BRW_PREDICATE_NORMAL : BRW_PREDICATE_NONE;
}
l.reg_offset++;
if (ir->write_mask & (1 << i)) {
inst = emit(BRW_OPCODE_MOV, l, r);
if (ir->condition)
- inst->predicated = true;
+ inst->predicate = BRW_PREDICATE_NORMAL;
r.reg_offset++;
}
l.reg_offset++;
emit_bool_to_cond_code(ir->condition);
inst = emit(BRW_OPCODE_IF);
- inst->predicated = true;
+ inst->predicate = BRW_PREDICATE_NORMAL;
}
foreach_list(node, &ir->then_instructions) {
inst->conditional_mod = brw_conditional_for_comparison(ir->cmp);
inst = emit(BRW_OPCODE_BREAK);
- inst->predicated = true;
+ inst->predicate = BRW_PREDICATE_NORMAL;
}
foreach_list(node, &ir->body_instructions) {
class backend_instruction : public exec_node {
public:
enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
+
+ uint32_t predicate;
+ bool predicate_inverse;
};
class backend_visitor : public ir_visitor {
src_reg src[3];
bool saturate;
- bool predicate_inverse;
- uint32_t predicate;
int conditional_mod; /**< BRW_CONDITIONAL_* */