Add tunning of ldpw for THunderX.

2016-09-12  Andrew Pinski  <apinski@cavium.com>

        * config/aarch64/aarch64-tuning-flags.def (SLOW_UNALIGNED_LDPW):
        New tuning option.
        * config/aarch64/aarch64.c (thunderx_tunings): Enable
        AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW.
        (aarch64_operands_ok_for_ldpstp): Return false if
        AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW and the mode
        was SImode and the alignment is less than 8 byte.
        (aarch64_operands_adjust_ok_for_ldpstp): Likewise.
2016-09-12  Andrew Pinski  <apinski@cavium.com>

        * gcc.target/aarch64/thunderxloadpair.c: New testcase.
        * gcc.target/aarch64/thunderxnoloadpair.c: New testcase.

From-SVN: r240102

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 1247b9083efd49a3b9a41baa65ba3f8c64b0bc64..2440b8f72ac0fa4bd1e41628cfa235232444e0c2 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+2016-09-12  Andrew Pinski  <apinski@cavium.com>
+
+       * config/aarch64/aarch64-tuning-flags.def (SLOW_UNALIGNED_LDPW):
+       New tuning option.
+       * config/aarch64/aarch64.c (thunderx_tunings): Enable
+       AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW.
+       (aarch64_operands_ok_for_ldpstp): Return false if
+       AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW and the mode
+       was SImode and the alignment is less than 8 byte.
+       (aarch64_operands_adjust_ok_for_ldpstp): Likewise.
+
 2016-09-12  Orlando Arias  <oarias@knights.ucf.edu>
 
        PR target/77570

diff --git a/gcc/config/aarch64/aarch64-tuning-flags.def b/gcc/config/aarch64/aarch64-tuning-flags.def
index 048c2a3e3f74beeaa9ff0bf0fd4c49c9a883e158..68b5ba0ad0eaf9568015f1bbdbb5447e73902477 100644 (file)
--- a/gcc/config/aarch64/aarch64-tuning-flags.def
+++ b/gcc/config/aarch64/aarch64-tuning-flags.def
@@ -29,3 +29,8 @@
      AARCH64_TUNE_ to give an enum name. */
 
 AARCH64_EXTRA_TUNING_OPTION ("rename_fma_regs", RENAME_FMA_REGS)
+
+/* Don't create non-8 byte aligned load/store pair.  That is if the
+two load/stores are not at least 8 byte aligned don't create load/store
+pairs.   */
+AARCH64_EXTRA_TUNING_OPTION ("slow_unaligned_ldpw", SLOW_UNALIGNED_LDPW)

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 2be750e7de4227bfdd4dd35f716f2344c824cc4a..3fcfaa88290bfb515ed984a0521432b74fdd3b2c 100644 (file)
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -712,7 +712,7 @@ static const struct tune_params thunderx_tunings =
   0,   /* max_case_values.  */
   0,   /* cache_line_size.  */
   tune_params::AUTOPREFETCHER_OFF,     /* autoprefetcher_model.  */
-  (AARCH64_EXTRA_TUNE_NONE)    /* tune_flags.  */
+  (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW)     /* tune_flags.  */
 };
 
 static const struct tune_params xgene1_tunings =
@@ -13629,6 +13629,15 @@ aarch64_operands_ok_for_ldpstp (rtx *operands, bool load,
   if (MEM_VOLATILE_P (mem_1) || MEM_VOLATILE_P (mem_2))
     return false;
 
+  /* If we have SImode and slow unaligned ldp,
+     check the alignment to be at least 8 byte. */
+  if (mode == SImode
+      && (aarch64_tune_params.extra_tuning_flags
+          & AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW)
+      && !optimize_size
+      && MEM_ALIGN (mem_1) < 8 * BITS_PER_UNIT)
+    return false;
+
   /* Check if the addresses are in the form of [base+offset].  */
   extract_base_offset_in_addr (mem_1, &base_1, &offset_1);
   if (base_1 == NULL_RTX || offset_1 == NULL_RTX)
@@ -13788,6 +13797,15 @@ aarch64_operands_adjust_ok_for_ldpstp (rtx *operands, bool load,
        return false;
     }
 
+  /* If we have SImode and slow unaligned ldp,
+     check the alignment to be at least 8 byte. */
+  if (mode == SImode
+      && (aarch64_tune_params.extra_tuning_flags
+          & AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW)
+      && !optimize_size
+      && MEM_ALIGN (mem_1) < 8 * BITS_PER_UNIT)
+    return false;
+
   if (REG_P (reg_1) && FP_REGNUM_P (REGNO (reg_1)))
     rclass_1 = FP_REGS;
   else

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 93cfbe5030dbb04a7ee1d35572d55ef8d985051d..9e59b031c574c75a60382f98425d07f2edbd01dc 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2016-09-12  Andrew Pinski  <apinski@cavium.com>
+
+       * gcc.target/aarch64/thunderxloadpair.c: New testcase.
+       * gcc.target/aarch64/thunderxnoloadpair.c: New testcase.
+
 2016-09-12  Uros Bizjak  <ubizjak@gmail.com>
 
        * gcc.dg/compat/scalar-by-value-4_x.c: Also test passing of

diff --git a/gcc/testsuite/gcc.target/aarch64/thunderxloadpair.c b/gcc/testsuite/gcc.target/aarch64/thunderxloadpair.c
new file mode 100644 (file)
index 0000000..14b1f73
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/thunderxloadpair.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mcpu=thunderx" } */
+
+struct ldp
+{
+  long long c;
+  int a, b;
+};
+
+
+int f(struct ldp *a)
+{
+  return a->a + a->b;
+}
+
+
+/* We know the alignement of a->a to be 8 byte aligned so it is profitable
+   to do ldp. */
+/* { dg-final { scan-assembler-times "ldp\tw\[0-9\]+, w\[0-9\]" 1 } } */
+

diff --git a/gcc/testsuite/gcc.target/aarch64/thunderxnoloadpair.c b/gcc/testsuite/gcc.target/aarch64/thunderxnoloadpair.c
new file mode 100644 (file)
index 0000000..3093ad0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/thunderxnoloadpair.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mcpu=thunderx" } */
+
+struct noldp
+{
+  int a, b;
+};
+
+
+int f(struct noldp *a)
+{
+  return a->a + a->b;
+}
+
+/* We know the alignement of a->a to be 4 byte aligned so it is not profitable
+   to do ldp. */
+/* { dg-final { scan-assembler-not "ldp\tw\[0-9\]+, w\[0-9\]" } } */