RISC-V: Add T-Head SYNC vendor extension

T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.

This patch adds the XTheadSync extension, a collection of
T-Head-specific multi-processor synchronization instructions.
The 'th' prefix and the "XTheadSync" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 82891f3747e04fc812873b34bf401a57086f7a00..ed516c2003b6fc0d4c49c1631e24fe665146e703 100644 (file)
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1225,6 +1225,7 @@ static struct riscv_supported_ext riscv_supported_std_zxm_ext[] =
 static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
 {
   {"xtheadcmo",                ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
+  {"xtheadsync",       ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
   {NULL, 0, 0, 0, 0}
 };
 
@@ -2389,6 +2390,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "h");
     case INSN_CLASS_XTHEADCMO:
       return riscv_subset_supports (rps, "xtheadcmo");
+    case INSN_CLASS_XTHEADSYNC:
+      return riscv_subset_supports (rps, "xtheadsync");
     default:
       rps->error_handler
         (_("internal: unreachable INSN_CLASS_*"));
@@ -2518,6 +2521,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("h");
     case INSN_CLASS_XTHEADCMO:
       return "xtheadcmo";
+    case INSN_CLASS_XTHEADSYNC:
+      return "xtheadsync";
     default:
       rps->error_handler
         (_("internal: unreachable INSN_CLASS_*"));

diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 10e9429c83e913e50ea178773b0f886859ef57e2..c55dd0b812e7a8c094b513a1b63ff9eb78297036 100644 (file)
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -709,4 +709,9 @@ The XTheadCmo extension provides instructions for cache management.
 
 It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}.
 
+@item XTheadSync
+The XTheadSync extension provides instructions for multi-processor synchronization.
+
+It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}.
+
 @end table

diff --git a/gas/testsuite/gas/riscv/x-thead-sync-fail.d b/gas/testsuite/gas/riscv/x-thead-sync-fail.d
new file mode 100644 (file)
index 0000000..1d3fdbd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-sync-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv64i_xtheadsync
+#source: x-thead-sync-fail.s
+#error_output: x-thead-sync-fail.l

diff --git a/gas/testsuite/gas/riscv/x-thead-sync-fail.l b/gas/testsuite/gas/riscv/x-thead-sync-fail.l
new file mode 100644 (file)
index 0000000..5242000
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-sync-fail.l
@@ -0,0 +1,6 @@
+.*: Assembler messages:
+.*: Error: illegal operands `th.sfence.vmas'
+.*: Error: illegal operands `th.sync a0'
+.*: Error: illegal operands `th.sync.i a0'
+.*: Error: illegal operands `th.sync.is a0'
+.*: Error: illegal operands `th.sync.s a0'

diff --git a/gas/testsuite/gas/riscv/x-thead-sync-fail.s b/gas/testsuite/gas/riscv/x-thead-sync-fail.s
new file mode 100644 (file)
index 0000000..722a6da
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-sync-fail.s
@@ -0,0 +1,6 @@
+target:
+       th.sfence.vmas
+       th.sync         a0
+       th.sync.i       a0
+       th.sync.is      a0
+       th.sync.s       a0

diff --git a/gas/testsuite/gas/riscv/x-thead-sync.d b/gas/testsuite/gas/riscv/x-thead-sync.d
new file mode 100644 (file)
index 0000000..3c5e9ea
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-sync.d
@@ -0,0 +1,14 @@
+#as: -march=rv64i_xtheadsync
+#source: x-thead-sync.s
+#objdump: -dr
+
+.*:[   ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[      ]+[0-9a-f]+:[   ]+04b5000b[     ]+th.sfence.vmas[       ]+a0,a1
+[      ]+[0-9a-f]+:[   ]+0180000b[     ]+th.sync
+[      ]+[0-9a-f]+:[   ]+01a0000b[     ]+th.sync.i
+[      ]+[0-9a-f]+:[   ]+01b0000b[     ]+th.sync.is
+[      ]+[0-9a-f]+:[   ]+0190000b[     ]+th.sync.s

diff --git a/gas/testsuite/gas/riscv/x-thead-sync.s b/gas/testsuite/gas/riscv/x-thead-sync.s
new file mode 100644 (file)
index 0000000..85b4856
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-sync.s
@@ -0,0 +1,6 @@
+target:
+       th.sfence.vmas  a0, a1
+       th.sync
+       th.sync.i
+       th.sync.is
+       th.sync.s

diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 53b1c224518be6c0cdbe38c1bb672d2d3e07bea8..970cdf22b255bc1886db59e8f24e3cc32cb8fed9 100644 (file)
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2156,6 +2156,17 @@
 #define MASK_TH_L2CACHE_CIALL 0xffffffff
 #define MATCH_TH_L2CACHE_IALL 0x0160000b
 #define MASK_TH_L2CACHE_IALL 0xffffffff
+/* Vendor-specific (T-Head) XTheadSync instructions.  */
+#define MATCH_TH_SFENCE_VMAS 0x0400000b
+#define MASK_TH_SFENCE_VMAS 0xfe007fff
+#define MATCH_TH_SYNC 0x0180000b
+#define MASK_TH_SYNC 0xffffffff
+#define MATCH_TH_SYNC_I 0x01a0000b
+#define MASK_TH_SYNC_I 0xffffffff
+#define MATCH_TH_SYNC_IS 0x01b0000b
+#define MASK_TH_SYNC_IS 0xffffffff
+#define MATCH_TH_SYNC_S 0x0190000b
+#define MASK_TH_SYNC_S 0xffffffff
 /* Unprivileged Counter/Timers CSR addresses.  */
 #define CSR_CYCLE 0xc00
 #define CSR_TIME 0xc01
@@ -2917,6 +2928,12 @@ DECLARE_INSN(th_icache_iva, MATCH_TH_ICACHE_IVA, MASK_TH_ICACHE_IVA)
 DECLARE_INSN(th_l2cache_call, MATCH_TH_L2CACHE_CALL, MASK_TH_L2CACHE_CALL)
 DECLARE_INSN(th_l2cache_ciall, MATCH_TH_L2CACHE_CIALL, MASK_TH_L2CACHE_CIALL)
 DECLARE_INSN(th_l2cache_iall, MATCH_TH_L2CACHE_IALL, MASK_TH_L2CACHE_IALL)
+/* Vendor-specific (T-Head) XTheadSync instructions.  */
+DECLARE_INSN(th_sfence_vmas, MATCH_TH_SFENCE_VMAS, MASK_TH_SFENCE_VMAS)
+DECLARE_INSN(th_sync, MATCH_TH_SYNC, MASK_TH_SYNC)
+DECLARE_INSN(th_sync_i, MATCH_TH_SYNC_I, MASK_TH_SYNC_I)
+DECLARE_INSN(th_sync_is, MATCH_TH_SYNC_IS, MASK_TH_SYNC_IS)
+DECLARE_INSN(th_sync_s, MATCH_TH_SYNC_S, MASK_TH_SYNC_S)
 #endif /* DECLARE_INSN */
 #ifdef DECLARE_CSR
 /* Unprivileged Counter/Timers CSRs.  */

diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index d36983140a204c5cc7b7d4b6eb0dfd01737f1401..6fdc9c9302e57d79ba711cb62defd317c178ea40 100644 (file)
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -399,6 +399,7 @@ enum riscv_insn_class
   INSN_CLASS_ZICBOZ,
   INSN_CLASS_H,
   INSN_CLASS_XTHEADCMO,
+  INSN_CLASS_XTHEADSYNC,
 };
 
 /* This structure holds information for a particular instruction.  */

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index bf073f20e71f0fd59cbda0c0fa535089b6df4708..8bba6487435f6653daaa1edf772fe53ed2bdb4d3 100644 (file)
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1850,6 +1850,13 @@ const struct riscv_opcode riscv_opcodes[] =
 {"th.l2cache.ciall", 0, INSN_CLASS_XTHEADCMO,   "",   MATCH_TH_L2CACHE_CIALL, MASK_TH_L2CACHE_CIALL, match_opcode, 0},
 {"th.l2cache.iall",  0, INSN_CLASS_XTHEADCMO,   "",   MATCH_TH_L2CACHE_IALL,  MASK_TH_L2CACHE_IALL,  match_opcode, 0},
 
+/* Vendor-specific (T-Head) XTheadSync instructions.  */
+{"th.sfence.vmas",   0, INSN_CLASS_XTHEADSYNC,  "s,t",MATCH_TH_SFENCE_VMAS,   MASK_TH_SFENCE_VMAS,   match_opcode, 0},
+{"th.sync",          0, INSN_CLASS_XTHEADSYNC,  "",   MATCH_TH_SYNC,          MASK_TH_SYNC,          match_opcode, 0},
+{"th.sync.i",        0, INSN_CLASS_XTHEADSYNC,  "",   MATCH_TH_SYNC_I,        MASK_TH_SYNC_I,        match_opcode, 0},
+{"th.sync.is",       0, INSN_CLASS_XTHEADSYNC,  "",   MATCH_TH_SYNC_IS,       MASK_TH_SYNC_IS,       match_opcode, 0},
+{"th.sync.s",        0, INSN_CLASS_XTHEADSYNC,  "",   MATCH_TH_SYNC_S,        MASK_TH_SYNC_S,        match_opcode, 0},
+
 /* Terminate the list.  */
 {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
 };