nv50,nvc0: stop limiting the number of active queries to 1
authorSamuel Pitoiset <samuel.pitoiset@gmail.com>
Wed, 26 Oct 2016 22:08:30 +0000 (00:08 +0200)
committerSamuel Pitoiset <samuel.pitoiset@gmail.com>
Wed, 2 Nov 2016 22:42:09 +0000 (23:42 +0100)
This limitation was initially here because AMD_performance_monitor
doesn't allow to expose the real number of hardware counters. But
this actually really annoying when profiling with qapitrace.

Anyways, performance counters are mostly for developers and
failures are expected if you try to monitor more queries than
supported.

This breaks amd_performance_monitor_measure but it's expected.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
src/gallium/drivers/nouveau/nv50/nv50_query.c
src/gallium/drivers/nouveau/nvc0/nvc0_query.c

index 9a1397a986016586e3f6777354ff6a40566a4206..e57e3ac8c3b3829434e764631df25c1602e1bb2e 100644 (file)
@@ -208,13 +208,11 @@ nv50_screen_get_driver_query_group_info(struct pipe_screen *pscreen,
          if (screen->base.class_3d >= NV84_3D_CLASS) {
             info->name = "MP counters";
 
-            /* Because we can't expose the number of hardware counters needed
-             * for each different query, we don't want to allow more than one
-             * active query simultaneously to avoid failure when the maximum
-             * number of counters is reached. Note that these groups of GPU
-             * counters are currently only used by AMD_performance_monitor.
-             */
-            info->max_active_queries = 1;
+            /* Expose the maximum number of hardware counters available,
+             * although some queries use more than one counter. Expect failures
+             * in that case but as performance counters are for developers,
+             * this should not have a real impact. */
+            info->max_active_queries = 4;
             info->num_queries = NV50_HW_SM_QUERY_COUNT;
             return 1;
          }
@@ -224,7 +222,7 @@ nv50_screen_get_driver_query_group_info(struct pipe_screen *pscreen,
       if (screen->compute) {
          if (screen->base.class_3d >= NV84_3D_CLASS) {
             info->name = "Performance metrics";
-            info->max_active_queries = 1;
+            info->max_active_queries = 2; /* A metric uses at least 2 queries */
             info->num_queries = NV50_HW_METRIC_QUERY_COUNT;
             return 1;
          }
index 91fb72f90b567b4be8d24b1c510b73c6d438a7ef..8b9e6b69d3ec40a9738c84731f542c5bdffe4620 100644 (file)
@@ -218,13 +218,11 @@ nvc0_screen_get_driver_query_group_info(struct pipe_screen *pscreen,
       if (screen->compute) {
          info->name = "MP counters";
 
-         /* Because we can't expose the number of hardware counters needed for
-          * each different query, we don't want to allow more than one active
-          * query simultaneously to avoid failure when the maximum number of
-          * counters is reached. Note that these groups of GPU counters are
-          * currently only used by AMD_performance_monitor.
-          */
-         info->max_active_queries = 1;
+         /* Expose the maximum number of hardware counters available, although
+          * some queries use more than one counter. Expect failures in that
+          * case but as performance counters are for developers, this should
+          * not have a real impact. */
+         info->max_active_queries = 8;
          info->num_queries = nvc0_hw_sm_get_num_queries(screen);
          return 1;
       }
@@ -233,7 +231,7 @@ nvc0_screen_get_driver_query_group_info(struct pipe_screen *pscreen,
       if (screen->compute) {
           if (screen->base.class_3d <= NVF0_3D_CLASS) {
             info->name = "Performance metrics";
-            info->max_active_queries = 1;
+            info->max_active_queries = 4; /* A metric uses at least 2 queries */
             info->num_queries = nvc0_hw_metric_get_num_queries(screen);
             return 1;
          }