enabled(false), haveGem5Extensions(p->gem5_extensions),
itLines(p->it_lines),
intEnabled {}, pendingInt {}, activeInt {},
- intPriority {}, cpuTarget {}, intConfig {},
+ intPriority {}, intConfig {}, cpuTarget {},
cpuSgiPending {}, cpuSgiActive {},
cpuSgiPendingExt {}, cpuSgiActiveExt {},
cpuPpiPending {}, cpuPpiActive {},
}
}
+ /** 2 bit per interrupt signaling if it's level or edge sensitive
+ * and if it is 1:N or N:N */
+ uint32_t intConfig[INT_BITS_MAX*2];
+
/** GICD_ICFGRn
* get 2 bit config associated to an interrupt.
*/
}
}
- /** 2 bit per interrupt signaling if it's level or edge sensitive
- * and if it is 1:N or N:N */
- uint32_t intConfig[INT_BITS_MAX*2];
-
bool isLevelSensitive(ContextID ctx, uint32_t ix) {
if (ix == SPURIOUS_INT) {
return false;