ARM: Decode the ssub instructions.

diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa
index 28fb5019455505417da6fdb7fbaa2d6fec73d0b9..648e04453e5e9ffe573e2ce2af93bd3d647fb78f 100644 (file)
--- a/src/arch/arm/isa/formats/data.isa
+++ b/src/arch/arm/isa/formats/data.isa
@@ -240,11 +240,11 @@ def format ArmParallelAddSubtract() {{
                   case 0x2:
                     return new WarnUnimplemented("ssax", machInst);
                   case 0x3:
-                    return new WarnUnimplemented("ssub16", machInst);
+                    return new Ssub16RegCc(machInst, rd, rn, rm, 0, LSL);
                   case 0x4:
                     return new Sadd8RegCc(machInst, rd, rn, rm, 0, LSL);
                   case 0x7:
-                    return new WarnUnimplemented("ssub8", machInst);
+                    return new Ssub8RegCc(machInst, rd, rn, rm, 0, LSL);
                 }
                 break;
               case 0x2:
@@ -557,12 +557,14 @@ def format Thumb32DataProcReg() {{
                           case 0x6:
                             return new WarnUnimplemented("ssax", machInst);
                           case 0x5:
-                            return new WarnUnimplemented("ssub16", machInst);
+                            return new Ssub16RegCc(machInst, rd,
+                                                   rn, rm, 0, LSL);
                           case 0x0:
                             return new Sadd8RegCc(machInst, rd,
                                                   rn, rm, 0, LSL);
                           case 0x4:
-                            return new WarnUnimplemented("ssub8", machInst);
+                            return new Ssub8RegCc(machInst, rd,
+                                                  rn, rm, 0, LSL);
                         }
                         break;
                       case 0x1: