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diff --git a/zfpacc_proposal.mdwn b/zfpacc_proposal.mdwn
index 4f2aea2fdcceaac4c8b7346a63c6aa3249df2fd1..2e21c0740c3bdec9693edabfbc39077876828e12 100644 (file)
--- a/zfpacc_proposal.mdwn
+++ b/zfpacc_proposal.mdwn
@@ -7,6 +7,7 @@ TODO: complete writeup
 
 Zfpacc: a proposal to allow implementations to dynamically set the bit-accuracy
 of results, trading speed (reduced latency) for accuracy (higher latency).
+IEE754 format is preserved: only ULP (Unit in Last Place) is permitted to be non-zero.
 
 # Extension of FCSR
 
@@ -86,6 +87,8 @@ The values for the field facc to include the following:
 | 0b100 | Vulkan  | Vulkan compliant    | 
 | 0b110 | Appx    | Machine Learning    |
 
+Note that the format of the operands and result remain the same for all opcodes. The only change is in the *accuracy* of the result, not its format.
+
 maybe a solution would be to add an extra field to the fp control csr
 to allow selecting one of several accurate or fast modes: