radeonsi: merge DCC/CMASK/HTILE priority flags

For a later simplification.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 76a3e0e441ae03bb68085ab79f46c8dcd9de4e18..57b82e7855f683868cac620e8bb556738fc73b33 100644 (file)
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1864,7 +1864,7 @@ static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r
                if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
                        cmask_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
                                tex->cmask_buffer, RADEON_USAGE_READWRITE,
-                               RADEON_PRIO_CMASK);
+                               RADEON_PRIO_SEPARATE_META);
                } else {
                        cmask_reloc = reloc;
                }
@@ -2053,7 +2053,7 @@ static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom
                radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
                radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
                reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource,
-                                                 RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
+                                                 RADEON_USAGE_READWRITE, RADEON_PRIO_SEPARATE_META);
                radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
                radeon_emit(cs, reloc_idx);
        } else {

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index d241d27d1b9735a5f21397dd30cba70829a1f585..9f3779f16d4c980b024e88d1d87c7a5edf9565dc 100644 (file)
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1554,7 +1554,7 @@ static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom
                radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
                radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
                reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource,
-                                                 RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
+                                                 RADEON_USAGE_READWRITE, RADEON_PRIO_SEPARATE_META);
                radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
                radeon_emit(cs, reloc_idx);
        } else {

diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index e9ae1f925c47e4417c6b519227ce62b962e35e81..bcd6831ed35253dd1f10d39620982d6c5e16f431 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -152,9 +152,7 @@ enum radeon_bo_priority {
 
     RADEON_PRIO_DEPTH_BUFFER_MSAA = 48,
 
-    RADEON_PRIO_CMASK = 52,
-    RADEON_PRIO_DCC,
-    RADEON_PRIO_HTILE,
+    RADEON_PRIO_SEPARATE_META = 52,
     RADEON_PRIO_SHADER_BINARY, /* the hw can't hide instruction cache misses */
 
     RADEON_PRIO_SHADER_RINGS = 56,

diff --git a/src/gallium/drivers/radeonsi/si_debug.c b/src/gallium/drivers/radeonsi/si_debug.c
index 0e5012b9d32249a1b614ad1b17aa7a5c32273e4f..50375ce7cbef015864ab40c86f9b487f94b229f1 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_debug.c
+++ b/src/gallium/drivers/radeonsi/si_debug.c
@@ -511,9 +511,7 @@ static const char *priority_to_string(enum radeon_bo_priority priority)
                ITEM(DEPTH_BUFFER),
                ITEM(COLOR_BUFFER_MSAA),
                ITEM(DEPTH_BUFFER_MSAA),
-               ITEM(CMASK),
-               ITEM(DCC),
-               ITEM(HTILE),
+               ITEM(SEPARATE_META),
                ITEM(SHADER_BINARY),
                ITEM(SHADER_RINGS),
                ITEM(SCRATCH_BUFFER),

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 83f62e4ac9317b80ea2c855218eef12a83c73e68..06e95e863eb16784f5ec2077ed2cd3ff7f575a6a 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -269,7 +269,7 @@ static void si_sampler_view_add_buffer(struct si_context *sctx,
        /* Add separate DCC. */
        if (tex->dcc_separate_buffer) {
                radeon_add_to_gfx_buffer_list_check_mem(sctx, tex->dcc_separate_buffer,
-                                                       usage, RADEON_PRIO_DCC, check_mem);
+                                                       usage, RADEON_PRIO_SEPARATE_META, check_mem);
        }
 }
 

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index a51b3739f03acdb56f1e2cd32c8ceace7d182108..7bbb1f63280bef9dffba02b246f45a5ec6c26cc0 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2997,14 +2997,14 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
                if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
                        radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
                                tex->cmask_buffer, RADEON_USAGE_READWRITE,
-                               RADEON_PRIO_CMASK);
+                               RADEON_PRIO_SEPARATE_META);
                }
 
                if (tex->dcc_separate_buffer)
                        radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
                                                  tex->dcc_separate_buffer,
                                                  RADEON_USAGE_READWRITE,
-                                                 RADEON_PRIO_DCC);
+                                                 RADEON_PRIO_SEPARATE_META);
 
                /* Compute mutable surface parameters. */
                cb_color_base = tex->buffer.gpu_address >> 8;