#include "sim/faults.hh"
#include "arch/isa_traits.hh" //For the Addr type
-class Garbage;
-class Fault;
-
class AlphaFault : public Fault
{
public:
//Outputs to decoder.hh
output header {{
+#define R31 31
+
/**
* Base class for all MIPS static instructions.
*/
// Bitfield definitions.
//
+def bitfield OPCODE <31:26>;
def bitfield OPCODE_HI <31:29>;
def bitfield OPCODE_LO <28:26>;
+def bitfield REGIMM <20:16>;
+def bitfield REGIMM_HI <20:19>;
+def bitfield REGIMM_LO <18:16>;
+
+def bitfield FUNCTION < 5: 0>;
def bitfield FUNCTION_HI < 5: 3>;
def bitfield FUNCTION_LO < 2: 0>;
def bitfield FS <15:11>;
def bitfield FD <10:6>;
+def bitfield ND <17:17>;
+def bitfield TF <16:16>;
def bitfield MOVCI <16:16>;
def bitfield MOVCF <16:16>;
def bitfield SRL <21:21>;
// Jmp format
def bitfield JMPTARG <25: 0>;
-def bitfield JMPHINT <10: 6>;
+def bitfield HINT <10: 6>;
def bitfield SYSCALLCODE <25: 6>;
def bitfield TRAPCODE <15:13>;
0x3: decode FUNCTION_LO {
format IntOp {
0x0: mult({{
- INT64 temp1 = Rs.sw * Rt.sw;
+ int64_t temp1 = Rs.sw * Rt.sw;
xc->miscRegs.hi->temp1<63:32>;
xc->miscRegs.lo->temp1<31:0>;
}});
0x1: multu({{
- INT64 temp1 = Rs.uw * Rt.uw;
+ int64_t temp1 = Rs.uw * Rt.uw;
xc->miscRegs.hi->temp1<63:32>;
xc->miscRegs.lo->temp1<31:0>
Rd.sw = Rs.uw * Rt.uw;
}
0x6: decode FUNCTION_LO {
- format Trap {
+ format BasicOp {
0x0: tge({{ cond = (Rs.sw >= Rt.sw); }});
0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }});
0x2: tlt({{ cond = (Rs.sw < Rt.sw); }});
}
0x1: decode REGIMM_LO {
- format Trap {
+ format BasicOp {
0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }});
0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }});
0x2: tlti( {{ cond = (Rs.sw < INTIMM); }});
0x2: decode REGIMM_LO {
format Branch {
- 0x0: bltzal({{ cond = (Rs.sw < 0); }}, IsLink);
- 0x1: bgezal({{ cond = (Rs.sw >= 0); }}, IsLink);
+ 0x0: bltzal({{ cond = (Rs.sw < 0); }}, IsCall,IsReturn);
+ 0x1: bgezal({{ cond = (Rs.sw >= 0); }}, IsCall,IsReturn);
}
format BranchLikely {
//Will be removed in future MIPS releases
- 0x2: bltzall({{ cond = (Rs.sw < 0); }}, IsLink);
- 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, IsLink);
+ 0x2: bltzall({{ cond = (Rs.sw < 0); }}, IsCall, IsReturn);
+ 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, IsCall, IsReturn);
}
}
//Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
0x1: decode FUNCTION {
- format Trap {
+ format BasicOp {
0x01: tlbr({{ }});
0x02: tlbwi({{ }});
0x06: tlbwr({{ }});
}
format Float64Op {
- 0x2: recips({{ Fd = 1 / Fs; }});
- 0x3: rsqrts({{ Fd = 1 / sqrt(Fs.ud);}});
+ 0x5: recips({{ Fd = 1 / Fs; }});
+ 0x6: rsqrts({{ Fd = 1 / sqrt(Fs.ud);}});
}
}
}
format BasicOp {
- 0x2: movz({{ if (Rt == 0) Fd.df = Fs.df; }});
- 0x3: movn({{ if (Rt != 0) Fd.df = Fs.df; }});
+ 0x2: movzd({{ if (Rt == 0) Fd.df = Fs.df; }});
+ 0x3: movnd({{ if (Rt != 0) Fd.df = Fs.df; }});
}
format Float64Op {
//Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W
0x4: decode FUNCTION {
format FloatOp {
- 0x10: cvt_s({{
+ 0x20: cvt_s({{
int rnd_mode = xc->miscRegs.fcsr;
Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_WORD);
}});
- 0x10: cvt_d({{
+ 0x21: cvt_d({{
int rnd_mode = xc->miscRegs.fcsr;
Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_WORD);
}});
}
}
+ format BasicOp {
+ 0x2: movzps({{ if ( FPConditionCode(CC) == 0) Fd = Fs; }});
+ 0x3: movnps({{ if ( FPConditionCode(CC) == 0) Fd = Fs; }});
+ }
+
}
0x4: decode RS_LO {
0x0: decode FUNCTION_LO {
format IntOp {
0x0: madd({{
- INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32;
+ int64_t temp1 = Hi.sw << 32 | Lo.sw >> 32;
temp1 = temp1 + (Rs.sw * Rt.sw);
xc->miscRegs.hi->temp1<63:32>;
xc->miscRegs.lo->temp1<31:0>
}});
0x1: maddu({{
- INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32;
+ int64_t temp1 = Hi.uw << 32 | Lo.uw >> 32;
temp1 = temp1 + (Rs.uw * Rt.uw);
xc->miscRegs.hi->temp1<63:32>;
xc->miscRegs.lo->temp1<31:0>
0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }});
0x4: msub({{
- INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32;
+ int64_t temp1 = Hi.sw << 32 | Lo.sw >> 32;
temp1 = temp1 - (Rs.sw * Rt.sw);
xc->miscRegs.hi->temp1<63:32>;
xc->miscRegs.lo->temp1<31:0>
}});
0x5: msubu({{
- INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32;
+ int64_t temp1 = Hi.uw << 32 | Lo.uw >> 32;
temp1 = temp1 - (Rs.uw * Rt.uw);
xc->miscRegs.hi->temp1<63:32>;
xc->miscRegs.lo->temp1<31:0>
//Include utility formats/functions
##include "m5/arch/mips/isa/formats/util.isa"
-//Include the integerOp and integerOpCc format
+//Include the integer formats
##include "m5/arch/mips/isa/formats/int.isa"
//Include the floatOp format
//Include the noop format
##include "m5/arch/mips/isa/formats/unknown.isa"
-
int32_t disp;
/// Constructor.
- Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
+ BranchLikely(const char *mnem, MachInst _machInst, OpClass __opClass)
: PCDependentDisassembly(mnem, _machInst, __opClass),
disp(OFFSET << 2)
{
ss << ",";
}
- ccprintf(ss, "(r%d)", RB);
+ ccprintf(ss, "(r%d)", RT);
return ss.str();
}
+// -*- mode:c++ -*-
+
////////////////////////////////////////////////////////////////////
//
// Floating Point operate instructions
output header {{
/**
- * Base class for integer operations.
+ * Base class for FP operations.
*/
class FPOp : public MipsStaticInst
{
}};
// Primary format for integer operate instructions:
-def format FloatOp(code, *opt_flags) {{
- orig_code = code
- cblk = CodeBlock(code)
- checkPriv = (code.find('checkPriv') != -1)
- code.replace('checkPriv', '')
- if checkPriv:
- code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
- else:
- code.replace('checkPriv;', '')
- for (marker, value) in (('ivValue', '0'), ('icValue', '0'),
- ('xvValue', '0'), ('xcValue', '0')):
- code.replace(marker, value)
- iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
+def format FloatOp(code, *flags) {{
+ iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
- decode_block = BasicDecodeWithMnemonic.subst(iop)
- exec_output = FloatingPointExecute.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
}};
// Primary format for integer operate instructions:
-def format Float64Op(code, *opt_flags) {{
- orig_code = code
- cblk = CodeBlock(code)
- checkPriv = (code.find('checkPriv') != -1)
- code.replace('checkPriv', '')
- if checkPriv:
- code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
- else:
- code.replace('checkPriv;', '')
- for (marker, value) in (('ivValue', '0'), ('icValue', '0'),
- ('xvValue', '0'), ('xcValue', '0')):
- code.replace(marker, value)
- iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- decode_block = BasicDecodeWithMnemonic.subst(iop)
- exec_output = FloatingPointExecute.subst(iop)
-}};
-
-// Primary format for integer operate instructions:
-def format FPOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
- orig_code = code
-
- cblk = CodeBlock(code)
- checkPriv = (code.find('checkPriv') != -1)
- code.replace('checkPriv', '')
- if checkPriv:
- code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
- else:
- code.replace('checkPriv;', '')
- for (marker, value) in (('ivValue', ivValue), ('icValue', icValue),
- ('xvValue', xvValue), ('xcValue', xcValue)):
- code.replace(marker, value)
- iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
+def format Float64Op(code, *flags) {{
+ iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
- decode_block = BasicDecodeWithMnemonic.subst(iop)
- exec_output = IntegerExecute.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
}};
Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
- flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB);
+ flags[IsFloating] ? 'f' : 'r', RS, JMPTARG, RT);
}
}};
}
}};
-// integer & FP operate instructions use Rc as dest, so check for
-// Rc == 31 to detect nops
+// integer & FP operate instructions use RT as dest, so check for
+// RT == 0 to detect nops
def template OperateNopCheckDecode {{
{
MipsStaticInst *i = new %(class_name)s(machInst);
- if (RC == 31) {
+ if (RD == 0) {
i = makeNop(i);
}
return i;
#include <iomanip>
#include "cpu/static_inst.hh"
-#include "traps.hh"
#include "mem/mem_req.hh" // some constructors use MemReq flags
}};
{
typedef uint32_t MachInst;
-// typedef uint64_t Addr;
+// typedef uint64_t Addr;
typedef uint8_t RegIndex;
enum {
IsCall, ///< Subroutine call.
IsReturn, ///< Subroutine return.
+ IsCondDelaySlot,///< Conditional Delay-Slot Instruction
+
IsThreadSync, ///< Thread synchronization operation.
IsSerializing, ///< Serializes pipeline: won't execute until all