pipistrello: add por reset counter

* this is a temporary fix that should be removed once the
combination of bitstream-in-flash, mor1kx, bios-in-flash works

diff --git a/targets/pipistrello.py b/targets/pipistrello.py
index ccdd499937eae91c85be28803c0d6c1cf9ef19b2..68e877f77d50d98e6261e03ab4d8ee0c60d3962e 100644 (file)
--- a/targets/pipistrello.py
+++ b/targets/pipistrello.py
@@ -58,7 +58,12 @@ class _CRG(Module):
                )
                self.specials += Instance("BUFG", i_I=pll[5], o_O=self.cd_sys.clk)
                reset = platform.request("user_btn")
-               self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd | reset)
+               self.clock_domains.cd_por = ClockDomain()
+               por = Signal(max=1 << 11, reset=(1 << 11) - 1)
+               self.sync.por += If(por != 0, por.eq(por - 1))
+               self.comb += self.cd_por.clk.eq(self.cd_sys.clk)
+               self.specials += AsyncResetSynchronizer(self.cd_por, reset)
+               self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd | (por > 0))
                self.specials += Instance("BUFG", i_I=pll[2], o_O=self.cd_sdram_half.clk)
                self.specials += Instance("BUFPLL", p_DIVIDE=4,
                                                        i_PLLIN=pll[0], i_GCLK=self.cd_sys.clk,