r600g: Enable FMA on chips that support it

v2: Merge with PIPE_SHADER_CAP_DOUBLES
    Add CHIP_HEMLOCK

v3: only set the instruction on EG and CM

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
index 42384f6124de7c24480251142d2d11e60f4c9199..f4811c4feaa23384284de139a2391103d46bbad8 100644 (file)
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -542,14 +542,16 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, e
                }
        case PIPE_SHADER_CAP_SUPPORTED_IRS:
                return 0;
+       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
        case PIPE_SHADER_CAP_DOUBLES:
-               if (rscreen->b.family == CHIP_CYPRESS ||
-                       rscreen->b.family == CHIP_CAYMAN || rscreen->b.family == CHIP_ARUBA)
+               if (rscreen->b.family == CHIP_ARUBA ||
+                   rscreen->b.family == CHIP_CAYMAN ||
+                   rscreen->b.family == CHIP_CYPRESS ||
+                   rscreen->b.family == CHIP_HEMLOCK)
                        return 1;
                return 0;
        case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
        case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
-       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
        case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
        case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
                return 0;

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 101f666f6837e3ed75215629fcced43ff474185e..9a1008e70c5ac06c33f455f39e184300895c85d8 100644 (file)
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -9116,7 +9116,7 @@ static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] =
        [TGSI_OPCODE_MAD]       = { ALU_OP3_MULADD, tgsi_op3},
        [TGSI_OPCODE_SUB]       = { ALU_OP2_ADD, tgsi_op2},
        [TGSI_OPCODE_LRP]       = { ALU_OP0_NOP, tgsi_lrp},
-       [TGSI_OPCODE_FMA]       = { ALU_OP0_NOP, tgsi_unsupported},
+       [TGSI_OPCODE_FMA]       = { ALU_OP3_FMA, tgsi_op3},
        [TGSI_OPCODE_SQRT]      = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
        [TGSI_OPCODE_DP2A]      = { ALU_OP0_NOP, tgsi_unsupported},
        [22]                    = { ALU_OP0_NOP, tgsi_unsupported},
@@ -9338,7 +9338,7 @@ static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] =
        [TGSI_OPCODE_MAD]       = { ALU_OP3_MULADD, tgsi_op3},
        [TGSI_OPCODE_SUB]       = { ALU_OP2_ADD, tgsi_op2},
        [TGSI_OPCODE_LRP]       = { ALU_OP0_NOP, tgsi_lrp},
-       [TGSI_OPCODE_FMA]       = { ALU_OP0_NOP, tgsi_unsupported},
+       [TGSI_OPCODE_FMA]       = { ALU_OP3_FMA, tgsi_op3},
        [TGSI_OPCODE_SQRT]      = { ALU_OP1_SQRT_IEEE, cayman_emit_float_instr},
        [TGSI_OPCODE_DP2A]      = { ALU_OP0_NOP, tgsi_unsupported},
        [22]                    = { ALU_OP0_NOP, tgsi_unsupported},