platforms/kc705: remove DDR3 multirank pins

diff --git a/mibuild/platforms/kc705.py b/mibuild/platforms/kc705.py
index 8dc4f7f6e81a8c0252103c4af3a034d8cc08eaf4..7be5635c641fff4c8fe1f47d21156f550da38bd7 100644 (file)
--- a/mibuild/platforms/kc705.py
+++ b/mibuild/platforms/kc705.py
@@ -88,12 +88,10 @@ _io = [
                        "AK13 AK14 AF13 AE13 AJ11 AH11 AK10 AK11"),
                        IOStandard("SSTL15")),
                Subsignal("ba", Pins("AH9 AG9 AK9"), IOStandard("SSTL15")),
-               Subsignal("cke", Pins("AF10 AE10"), IOStandard("SSTL15")),
                Subsignal("ras_n", Pins("AD9"), IOStandard("SSTL15")),
                Subsignal("cas_n", Pins("AC11"), IOStandard("SSTL15")),
                Subsignal("we_n", Pins("AE9"), IOStandard("SSTL15")),
-               Subsignal("cs_n", Pins("AC12 AE8"), IOStandard("SSTL15")),
-               Subsignal("odt", Pins("AD8 AC10"), IOStandard("SSTL15")),
+               Subsignal("cs_n", Pins("AC12"), IOStandard("SSTL15")),
                Subsignal("dm", Pins("Y16 AB17 AF17 AE16 AK5 AJ3 AF6 AC7"),
                        IOStandard("SSTL15")),
                Subsignal("dq", Pins(
@@ -112,7 +110,9 @@ _io = [
                        IOStandard("DIFF_SSTL15")),
                Subsignal("clk_p", Pins("AG10"), IOStandard("DIFF_SSTL15")),
                Subsignal("clk_n", Pins("AH10"), IOStandard("DIFF_SSTL15")),
-               Subsignal("rst_n", Pins("AK3"), IOStandard("LVCMOS15")),
+               Subsignal("cke", Pins("AF10"), IOStandard("SSTL15")),
+               Subsignal("odt", Pins("AD8"), IOStandard("SSTL15")),
+               Subsignal("reset_n", Pins("AK3"), IOStandard("LVCMOS15")),
                Misc("SLEW=FAST"),
                Misc("VCCAUX_IO=HIGH")
        ),