(no commit message)

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index 88ac14d4716c3a4e75dbc3e50a47286b11a0c2f4..20ad7d32500bae9df40a176d0160e643108303e5 100644 (file)
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -149,6 +149,8 @@ When Rc=1 is encountered in an SVP64 Context the destination is different (TODO)
 
 TODO.  INTs, FPs, CRs, these all increase to 128.  Welcome To Vector ISAs.
 
+At the same time the `Rc=1` CR offsets normslly CR0 and CR1 for fixed and FP svslar may also be adjusted.
+
 ## Single Predication
 
 TODO