arch-riscv: added (un)serialization of miscRegFile.

Change-Id: I127dbf4a6bb4a144eaee05a87495830dce82eb58
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25650
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 3f1a7e1af715dc5d9f3d4312000c81cf727ff05e..754ff85b758a41d4ea2c0fb70aac23cc324d6ff0 100644 (file)
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -39,6 +39,7 @@
 #include "arch/riscv/registers.hh"
 #include "base/bitfield.hh"
 #include "cpu/base.hh"
+#include "debug/Checkpoint.hh"
 #include "debug/RiscvMisc.hh"
 #include "params/RiscvISA.hh"
 #include "sim/core.hh"
@@ -352,6 +353,20 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
     }
 }
 
+void
+ISA::serialize(CheckpointOut &cp) const
+{
+    DPRINTF(Checkpoint, "Serializing Riscv Misc Registers\n");
+    SERIALIZE_CONTAINER(miscRegFile);
+}
+
+void
+ISA::unserialize(CheckpointIn &cp)
+{
+    DPRINTF(Checkpoint, "Unserializing Riscv Misc Registers\n");
+    UNSERIALIZE_CONTAINER(miscRegFile);
+}
+
 }
 
 RiscvISA::ISA *

diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index 9d342428cad45ac07f7675bb90a07ffa76244aea..c56c45ba7ae8b396122ba6264f93f5ad0bb3c356 100644 (file)
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -92,6 +92,9 @@ class ISA : public BaseISA
 
     void startup(ThreadContext *tc) {}
 
+    void serialize(CheckpointOut &cp) const;
+    void unserialize(CheckpointIn &cp);
+
     /// Explicitly import the otherwise hidden startup
     using BaseISA::startup;