i965: Don't set a nonexistent enable bit in several SNB state pointers.
authorEric Anholt <eric@anholt.net>
Fri, 26 Feb 2010 00:25:17 +0000 (16:25 -0800)
committerEric Anholt <eric@anholt.net>
Fri, 26 Feb 2010 02:36:44 +0000 (18:36 -0800)
The modify bit is now usually in the instruction header.  The
exception is CC state pointers.

src/mesa/drivers/dri/i965/gen6_sampler_state.c
src/mesa/drivers/dri/i965/gen6_scissor_state.c
src/mesa/drivers/dri/i965/gen6_viewport_state.c

index 641d8859b3a39b7befc90327c7d913308a02d32c..f5d537b1cfbe347df3db7b0300e1f1baccaeca35 100644 (file)
@@ -47,7 +47,7 @@ upload_sampler_state_pointers(struct brw_context *brw)
    OUT_BATCH(0); /* VS */
    OUT_BATCH(0); /* GS */
    if (brw->wm.sampler_bo)
-      OUT_RELOC(brw->wm.sampler_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
+      OUT_RELOC(brw->wm.sampler_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
    else
       OUT_BATCH(0);
 
index 2d36f0056d9ffd9ebafcbbbda2d812b49f3ec840..81ebbf4ddf399095b3eb875b6266a766ce67139b 100644 (file)
@@ -85,7 +85,7 @@ static void upload_scissor_state_pointers(struct brw_context *brw)
 
    BEGIN_BATCH(2);
    OUT_BATCH(CMD_3D_SCISSOR_STATE_POINTERS << 16 | (2 - 2));
-   OUT_RELOC(brw->sf.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
+   OUT_RELOC(brw->sf.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
    ADVANCE_BATCH();
 
    intel_batchbuffer_emit_mi_flush(intel->batch);
index 13d2fc1b42b1e43a0d581505d6a94dbd64464ace..df3cbfb22457456c9e8b35b26fc363a49d98ea96 100644 (file)
@@ -154,9 +154,9 @@ static void upload_viewport_state_pointers(struct brw_context *brw)
             GEN6_CC_VIEWPORT_MODIFY |
             GEN6_SF_VIEWPORT_MODIFY |
             GEN6_CLIP_VIEWPORT_MODIFY);
-   OUT_RELOC(brw->clip.vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
-   OUT_RELOC(brw->sf.vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
-   OUT_RELOC(brw->cc.vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
+   OUT_RELOC(brw->clip.vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+   OUT_RELOC(brw->sf.vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+   OUT_RELOC(brw->cc.vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
    ADVANCE_BATCH();
 
    intel_batchbuffer_emit_mi_flush(intel->batch);