radeonsi: Reinitialize all descriptors in CE preamble.

This fixes a problem with the CE preamble and restoring only stuff in the
preamble when needed.

To illustrate suppose we have two graphics IB's 1 and 2, which  are submitted in
that order. Furthermore suppose IB 1 does not use CE ram, but IB 2 does, and we
have a context switch at the start of IB 1, but not between IB 1 and IB 2.

The old code put the CE RAM loads in the preamble of IB 2. As the preamble of
IB 1 does not have the loads and the preamble of IB 2 does not get executed, the
old values are not load into CE RAM.

Fix this by always restoring the entire CE RAM.

v2: - Just load all descriptor set buffers instead of load and store the entire
      CE RAM.
    - Leave the ce_ram_dirty tracking in place for the non-preamble case.

v3: - Fixed parameter alignment.
    - Rebased to master (Nicolai's descriptor series).

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index e80db3950758234507513ca8c85b23cb89593a77..2d780e6e46953862c535d9e3ed3f892bb2ebb03f 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -160,8 +160,8 @@ static bool si_ce_upload(struct si_context *sctx, unsigned ce_offset, unsigned s
        return true;
 }
 
-static void si_reinitialize_ce_ram(struct si_context *sctx,
-                            struct si_descriptors *desc)
+static void si_ce_reinitialize_descriptors(struct si_context *sctx,
+                                           struct si_descriptors *desc)
 {
        if (desc->buffer) {
                struct r600_resource *buffer = (struct r600_resource*)desc->buffer;
@@ -186,6 +186,14 @@ static void si_reinitialize_ce_ram(struct si_context *sctx,
        desc->ce_ram_dirty = false;
 }
 
+void si_ce_reinitialize_all_descriptors(struct si_context *sctx)
+{
+       int i;
+
+       for (i = 0; i < SI_NUM_DESCS; ++i)
+               si_ce_reinitialize_descriptors(sctx, &sctx->descriptors[i]);
+}
+
 void si_ce_enable_loads(struct radeon_winsys_cs *ib)
 {
        radeon_emit(ib, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
@@ -207,7 +215,7 @@ static bool si_upload_descriptors(struct si_context *sctx,
                uint32_t const* list = (uint32_t const*)desc->list;
 
                if (desc->ce_ram_dirty)
-                       si_reinitialize_ce_ram(sctx, desc);
+                       si_ce_reinitialize_descriptors(sctx, desc);
 
                while(desc->dirty_mask) {
                        int begin, count;

diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c b/src/gallium/drivers/radeonsi/si_hw_context.c
index fa6a2cbef0b604988620977b3a9a4b2a0af94864..d1b98513e84895e5118ed7aa6c3dd51c0aff525e 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -213,6 +213,9 @@ void si_begin_new_cs(struct si_context *ctx)
        else if (ctx->ce_ib)
                si_ce_enable_loads(ctx->ce_ib);
 
+       if (ctx->ce_preamble_ib)
+               si_ce_reinitialize_all_descriptors(ctx);
+
        ctx->framebuffer.dirty_cbufs = (1 << 8) - 1;
        ctx->framebuffer.dirty_zsbuf = true;
        si_mark_atom_dirty(ctx, &ctx->framebuffer.atom);

diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
index a4a58bba9051a1221665caf5db155a78c3bcdbb5..ab34feca857ca8b0b2c69ec609c49ed3807a2182 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -276,6 +276,7 @@ struct si_buffer_resources {
        } while(0)
 
 /* si_descriptors.c */
+void si_ce_reinitialize_all_descriptors(struct si_context *sctx);
 void si_ce_enable_loads(struct radeon_winsys_cs *ib);
 void si_set_mutable_tex_desc_fields(struct r600_texture *tex,
                                    const struct radeon_surf_level *base_level_info,