+2019-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
+ Delete.
+ (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
+ of dqa_mode.
+ * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
+ entries here.
+ * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
+ entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
+
2019-06-25 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
/* PREFIX_EVEX_0F2A */
{
{ Bad_Opcode },
- { VEX_W_TABLE (EVEX_W_0F2A_P_1) },
+ { "vcvtsi2ss%LQ", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
{ Bad_Opcode },
{ VEX_W_TABLE (EVEX_W_0F2A_P_3) },
},
/* PREFIX_EVEX_0F7B */
{
{ Bad_Opcode },
- { VEX_W_TABLE (EVEX_W_0F7B_P_1) },
+ { "vcvtusi2ss%LQ", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
{ VEX_W_TABLE (EVEX_W_0F7B_P_2) },
{ VEX_W_TABLE (EVEX_W_0F7B_P_3) },
},
{ Bad_Opcode },
{ "vmovapd", { EXxS, XM }, 0 },
},
- /* EVEX_W_0F2A_P_1 */
- {
- { "vcvtsi2ss%LQ", { XMScalar, VexScalar, EXxEVexR, Ed }, 0 },
- { "vcvtsi2ss%LQ", { XMScalar, VexScalar, EXxEVexR, Edqa }, 0 },
- },
/* EVEX_W_0F2A_P_3 */
{
{ "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ed }, 0 },
- { "vcvtsi2sd%LQ", { XMScalar, VexScalar, EXxEVexR64, Edqa }, 0 },
+ { "vcvtsi2sd%LQ", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
},
/* EVEX_W_0F2B_P_0 */
{
{ "vcvtudq2ps", { XM, EXx, EXxEVexR }, 0 },
{ "vcvtuqq2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
},
- /* EVEX_W_0F7B_P_1 */
- {
- { "vcvtusi2ss%LQ", { XMScalar, VexScalar, EXxEVexR, Ed }, 0 },
- { "vcvtusi2ss%LQ", { XMScalar, VexScalar, EXxEVexR, Edqa }, 0 },
- },
/* EVEX_W_0F7B_P_2 */
{
{ "vcvtps2qq", { XM, EXEvexHalfBcstXmmq, EXxEVexR }, 0 },
/* EVEX_W_0F7B_P_3 */
{
{ "vcvtusi2sd%LQ", { XMScalar, VexScalar, Ed }, 0 },
- { "vcvtusi2sd%LQ", { XMScalar, VexScalar, EXxEVexR64, Edqa }, 0 },
+ { "vcvtusi2sd%LQ", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
},
/* EVEX_W_0F7E_P_1 */
{
#define Edb { OP_E, db_mode }
#define Edw { OP_E, dw_mode }
#define Edqd { OP_E, dqd_mode }
-#define Edqa { OP_E, dqa_mode }
#define Eq { OP_E, q_mode }
#define indirEv { OP_indirE, indir_v_mode }
#define indirEp { OP_indirE, f_mode }
dw_mode,
/* registers like dq_mode, memory like d_mode. */
dqd_mode,
- /* operand size depends on the W bit as well as address mode. */
- dqa_mode,
/* normal vex mode */
vex_mode,
/* 128bit vex mode */
EVEX_W_0F28_P_2,
EVEX_W_0F29_P_0,
EVEX_W_0F29_P_2,
- EVEX_W_0F2A_P_1,
EVEX_W_0F2A_P_3,
EVEX_W_0F2B_P_0,
EVEX_W_0F2B_P_2,
EVEX_W_0F7A_P_1,
EVEX_W_0F7A_P_2,
EVEX_W_0F7A_P_3,
- EVEX_W_0F7B_P_1,
EVEX_W_0F7B_P_2,
EVEX_W_0F7B_P_3,
EVEX_W_0F7E_P_1,
case q_swap_mode:
oappend ("QWORD PTR ");
break;
- case dqa_mode:
case m_mode:
if (address_mode == mode_64bit)
oappend ("QWORD PTR ");
case dqb_mode:
case dqd_mode:
case dqw_mode:
- case dqa_mode:
USED_REX (REX_W);
if (rex & REX_W)
names = names64;
case xmm_mb_mode:
shift = 0;
break;
- case dqa_mode:
- shift = address_mode == mode_64bit ? 3 : 2;
- break;
default:
abort ();
}