$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_sim.v))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/eagle_bb.v))
-$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams.txt))
-$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams_map.v))
-$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/dram_init_16x4.vh))
+$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutrams.txt))
+$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutrams_map.v))
+$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutram_init_16x4.vh))
+++ /dev/null
-.INIT_D0({INIT[15*4+0], INIT[14*4+0], INIT[13*4+0], INIT[12*4+0],
- INIT[11*4+0], INIT[10*4+0], INIT[9*4+0], INIT[8*4+0],
- INIT[7*4+0], INIT[6*4+0], INIT[5*4+0], INIT[4*4+0],
- INIT[3*4+0], INIT[2*4+0], INIT[1*4+0], INIT[0*4+0]}),
-.INIT_D1({INIT[15*4+1], INIT[14*4+1], INIT[13*4+1], INIT[12*4+1],
- INIT[11*4+1], INIT[10*4+1], INIT[9*4+1], INIT[8*4+1],
- INIT[7*4+1], INIT[6*4+1], INIT[5*4+1], INIT[4*4+1],
- INIT[3*4+1], INIT[2*4+1], INIT[1*4+1], INIT[0*4+1]}),
-.INIT_D2({INIT[15*4+2], INIT[14*4+2], INIT[13*4+2], INIT[12*4+2],
- INIT[11*4+2], INIT[10*4+2], INIT[9*4+2], INIT[8*4+2],
- INIT[7*4+2], INIT[6*4+2], INIT[5*4+2], INIT[4*4+2],
- INIT[3*4+2], INIT[2*4+2], INIT[1*4+2], INIT[0*4+2]}),
-.INIT_D3({INIT[15*4+3], INIT[14*4+3], INIT[13*4+3], INIT[12*4+3],
- INIT[11*4+3], INIT[10*4+3], INIT[9*4+3], INIT[8*4+3],
- INIT[7*4+3], INIT[6*4+3], INIT[5*4+3], INIT[4*4+3],
- INIT[3*4+3], INIT[2*4+3], INIT[1*4+3], INIT[0*4+3]})
+++ /dev/null
-bram $__ANLOGIC_DRAM16X4
- init 1
- abits 4
- dbits 4
- groups 2
- ports 1 1
- wrmode 0 1
- enable 0 1
- transp 0 0
- clocks 0 1
- clkpol 0 1
-endbram
-
-match $__ANLOGIC_DRAM16X4
- make_outreg
-endmatch
+++ /dev/null
-module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
- parameter [63:0]INIT = 64'bx;
- input CLK1;
-
- input [3:0] A1ADDR;
- output [3:0] A1DATA;
-
- input [3:0] B1ADDR;
- input [3:0] B1DATA;
- input B1EN;
-
- EG_LOGIC_DRAM16X4 #(
- `include "dram_init_16x4.vh"
- ) _TECHMAP_REPLACE_ (
- .di(B1DATA),
- .waddr(B1ADDR),
- .wclk(CLK1),
- .we(B1EN),
- .raddr(A1ADDR),
- .do(A1DATA)
- );
-endmodule
--- /dev/null
+.INIT_D0({INIT[15*4+0], INIT[14*4+0], INIT[13*4+0], INIT[12*4+0],
+ INIT[11*4+0], INIT[10*4+0], INIT[9*4+0], INIT[8*4+0],
+ INIT[7*4+0], INIT[6*4+0], INIT[5*4+0], INIT[4*4+0],
+ INIT[3*4+0], INIT[2*4+0], INIT[1*4+0], INIT[0*4+0]}),
+.INIT_D1({INIT[15*4+1], INIT[14*4+1], INIT[13*4+1], INIT[12*4+1],
+ INIT[11*4+1], INIT[10*4+1], INIT[9*4+1], INIT[8*4+1],
+ INIT[7*4+1], INIT[6*4+1], INIT[5*4+1], INIT[4*4+1],
+ INIT[3*4+1], INIT[2*4+1], INIT[1*4+1], INIT[0*4+1]}),
+.INIT_D2({INIT[15*4+2], INIT[14*4+2], INIT[13*4+2], INIT[12*4+2],
+ INIT[11*4+2], INIT[10*4+2], INIT[9*4+2], INIT[8*4+2],
+ INIT[7*4+2], INIT[6*4+2], INIT[5*4+2], INIT[4*4+2],
+ INIT[3*4+2], INIT[2*4+2], INIT[1*4+2], INIT[0*4+2]}),
+.INIT_D3({INIT[15*4+3], INIT[14*4+3], INIT[13*4+3], INIT[12*4+3],
+ INIT[11*4+3], INIT[10*4+3], INIT[9*4+3], INIT[8*4+3],
+ INIT[7*4+3], INIT[6*4+3], INIT[5*4+3], INIT[4*4+3],
+ INIT[3*4+3], INIT[2*4+3], INIT[1*4+3], INIT[0*4+3]})
--- /dev/null
+bram $__ANLOGIC_DRAM16X4
+ init 1
+ abits 4
+ dbits 4
+ groups 2
+ ports 1 1
+ wrmode 0 1
+ enable 0 1
+ transp 0 0
+ clocks 0 1
+ clkpol 0 1
+endbram
+
+match $__ANLOGIC_DRAM16X4
+ make_outreg
+endmatch
--- /dev/null
+module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+ parameter [63:0]INIT = 64'bx;
+ input CLK1;
+
+ input [3:0] A1ADDR;
+ output [3:0] A1DATA;
+
+ input [3:0] B1ADDR;
+ input [3:0] B1DATA;
+ input B1EN;
+
+ EG_LOGIC_DRAM16X4 #(
+ `include "lutram_init_16x4.vh"
+ ) _TECHMAP_REPLACE_ (
+ .di(B1DATA),
+ .waddr(B1ADDR),
+ .wclk(CLK1),
+ .we(B1EN),
+ .raddr(A1ADDR),
+ .do(A1DATA)
+ );
+endmodule
log(" -retime\n");
log(" run 'abc' with -dff option\n");
log("\n");
+ log(" -nolutram\n");
+ log(" do not use EG_LOGIC_DRAM16X4 cells in output netlist\n");
+ log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
help_script();
}
string top_opt, edif_file, json_file;
- bool flatten, retime;
+ bool flatten, retime, nolutram;
void clear_flags() YS_OVERRIDE
{
json_file = "";
flatten = true;
retime = false;
+ nolutram = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
flatten = false;
continue;
}
+ if (args[argidx] == "-nolutram") {
+ nolutram = true;
+ continue;
+ }
if (args[argidx] == "-retime") {
retime = true;
continue;
run("synth -run coarse");
}
- if (check_label("dram"))
+ if (!nolutram && check_label("map_lutram", "(skip if -nolutram)"))
{
- run("memory_bram -rules +/anlogic/drams.txt");
- run("techmap -map +/anlogic/drams_map.v");
+ run("memory_bram -rules +/anlogic/lutrams.txt");
+ run("techmap -map +/anlogic/lutrams_map.v");
run("setundef -zero -params t:EG_LOGIC_DRAM16X4");
}
- if (check_label("fine"))
+ if (check_label("map_ffram"))
{
run("opt -fast -mux_undef -undriven -fine");
run("memory_map");
run("opt -undriven -fine");
+ }
+
+ if (check_label("map_gates"))
+ {
run("techmap -map +/techmap.v -map +/anlogic/arith_map.v");
if (retime || help_mode)
run("abc -dff", "(only if -retime)");
run("techmap -map +/anlogic/cells_map.v");
run("clean");
}
-
+
if (check_label("map_anlogic"))
{
run("anlogic_fixcarry");
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_bb.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/lutrams_map.v))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/lutram.txt))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/lutrams.txt))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams_map.v))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams.txt))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dsp_map.v))
+++ /dev/null
-bram $__ECP5_PDPW16KD
- init 1
-
- abits 9
- dbits 36
-
- groups 2
- ports 1 1
- wrmode 1 0
- enable 4 1
- transp 0 0
- clocks 2 3
- clkpol 2 3
-endbram
-
-bram $__ECP5_DP16KD
- init 1
-
- abits 10 @a10d18
- dbits 18 @a10d18
- abits 11 @a11d9
- dbits 9 @a11d9
- abits 12 @a12d4
- dbits 4 @a12d4
- abits 13 @a13d2
- dbits 2 @a13d2
- abits 14 @a14d1
- dbits 1 @a14d1
-
- groups 2
- ports 1 1
- wrmode 1 0
- enable 2 1 @a10d18
- enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
- transp 0 2
- clocks 2 3
- clkpol 2 3
-endbram
-
-match $__ECP5_PDPW16KD
- min bits 2048
- min efficiency 5
- shuffle_enable A
- make_transp
- or_next_if_better
-endmatch
-
-match $__ECP5_DP16KD
- min bits 2048
- min efficiency 5
- shuffle_enable A
-endmatch
--- /dev/null
+bram $__ECP5_PDPW16KD
+ init 1
+
+ abits 9
+ dbits 36
+
+ groups 2
+ ports 1 1
+ wrmode 1 0
+ enable 4 1
+ transp 0 0
+ clocks 2 3
+ clkpol 2 3
+endbram
+
+bram $__ECP5_DP16KD
+ init 1
+
+ abits 10 @a10d18
+ dbits 18 @a10d18
+ abits 11 @a11d9
+ dbits 9 @a11d9
+ abits 12 @a12d4
+ dbits 4 @a12d4
+ abits 13 @a13d2
+ dbits 2 @a13d2
+ abits 14 @a14d1
+ dbits 1 @a14d1
+
+ groups 2
+ ports 1 1
+ wrmode 1 0
+ enable 2 1 @a10d18
+ enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
+ transp 0 2
+ clocks 2 3
+ clkpol 2 3
+endbram
+
+match $__ECP5_PDPW16KD
+ min bits 2048
+ min efficiency 5
+ shuffle_enable A
+ make_transp
+ or_next_if_better
+endmatch
+
+match $__ECP5_DP16KD
+ min bits 2048
+ min efficiency 5
+ shuffle_enable A
+endmatch
+++ /dev/null
-bram $__TRELLIS_DPR16X4
- init 1
- abits 4
- dbits 4
- groups 2
- ports 1 1
- wrmode 0 1
- enable 0 1
- transp 0 0
- clocks 0 1
- clkpol 0 2
-endbram
-
-match $__TRELLIS_DPR16X4
- make_outreg
- min wports 1
-endmatch
--- /dev/null
+bram $__TRELLIS_DPR16X4
+ init 1
+ abits 4
+ dbits 4
+ groups 2
+ ports 1 1
+ wrmode 0 1
+ enable 0 1
+ transp 0 0
+ clocks 0 1
+ clkpol 0 2
+endbram
+
+match $__TRELLIS_DPR16X4
+ make_outreg
+ min wports 1
+endmatch
if (!nobram && check_label("map_bram", "(skip if -nobram)"))
{
- run("memory_bram -rules +/ecp5/bram.txt");
+ run("memory_bram -rules +/ecp5/brams.txt");
run("techmap -map +/ecp5/brams_map.v");
}
if (!nolutram && check_label("map_lutram", "(skip if -nolutram)"))
{
- run("memory_bram -rules +/ecp5/lutram.txt");
+ run("memory_bram -rules +/ecp5/lutrams.txt");
run("techmap -map +/ecp5/lutrams_map.v");
}
$(eval $(call add_share_file,share/efinix,techlibs/efinix/arith_map.v))
$(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_sim.v))
$(eval $(call add_share_file,share/efinix,techlibs/efinix/brams_map.v))
-$(eval $(call add_share_file,share/efinix,techlibs/efinix/bram.txt))
+$(eval $(call add_share_file,share/efinix,techlibs/efinix/brams.txt))
+++ /dev/null
-bram $__EFINIX_5K
- init 1
-
- abits 8 @a8d16
- dbits 16 @a8d16
- abits 9 @a9d8
- dbits 8 @a9d8
- abits 10 @a10d4
- dbits 4 @a10d4
- abits 11 @a11d2
- dbits 2 @a11d2
- abits 12 @a12d1
- dbits 1 @a12d1
- abits 8 @a8d20
- dbits 20 @a8d20
- abits 9 @a9d10
- dbits 10 @a9d10
-
- groups 2
- ports 1 1
- wrmode 1 0
- enable 1 1
- transp 0 2
- clocks 2 3
- clkpol 2 3
-endbram
-
-match $__EFINIX_5K
- min bits 256
- min efficiency 5
- shuffle_enable B
-endmatch
--- /dev/null
+bram $__EFINIX_5K
+ init 1
+
+ abits 8 @a8d16
+ dbits 16 @a8d16
+ abits 9 @a9d8
+ dbits 8 @a9d8
+ abits 10 @a10d4
+ dbits 4 @a10d4
+ abits 11 @a11d2
+ dbits 2 @a11d2
+ abits 12 @a12d1
+ dbits 1 @a12d1
+ abits 8 @a8d20
+ dbits 20 @a8d20
+ abits 9 @a9d10
+ dbits 10 @a9d10
+
+ groups 2
+ ports 1 1
+ wrmode 1 0
+ enable 1 1
+ transp 0 2
+ clocks 2 3
+ clkpol 2 3
+endbram
+
+match $__EFINIX_5K
+ min bits 256
+ min efficiency 5
+ shuffle_enable B
+endmatch
log(" -retime\n");
log(" run 'abc' with -dff option\n");
log("\n");
+ log(" -nobram\n");
+ log(" do not use EFX_RAM_5K cells in output netlist\n");
+ log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
help_script();
}
string top_opt, edif_file, json_file;
- bool flatten, retime;
+ bool flatten, retime, nobram;
void clear_flags() YS_OVERRIDE
{
json_file = "";
flatten = true;
retime = false;
+ nobram = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
retime = true;
continue;
}
+ if (args[argidx] == "-nobram") {
+ nobram = true;
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
run("synth -run coarse");
}
- if (check_label("map_bram", "(skip if -nobram)"))
+ if (!nobram || check_label("map_bram", "(skip if -nobram)"))
{
- run("memory_bram -rules +/efinix/bram.txt");
+ run("memory_bram -rules +/efinix/brams.txt");
run("techmap -map +/efinix/brams_map.v");
run("setundef -zero -params t:EFX_RAM_5K");
}
- if (check_label("fine"))
+ if (check_label("map_ffram"))
{
run("opt -fast -mux_undef -undriven -fine");
run("memory_map");
run("opt -undriven -fine");
+ }
+
+ if (check_label("map_gates"))
+ {
run("techmap -map +/techmap.v -map +/efinix/arith_map.v");
if (retime || help_mode)
run("abc -dff", "(only if -retime)");
run("efinix_fixcarry");
run("clean");
}
-
+
if (check_label("check"))
{
run("hierarchy -check");
$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_sim.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/arith_map.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_map.v))
-$(eval $(call add_share_file,share/gowin,techlibs/gowin/bram.txt))
-$(eval $(call add_share_file,share/gowin,techlibs/gowin/drams_map.v))
-$(eval $(call add_share_file,share/gowin,techlibs/gowin/dram.txt))
+$(eval $(call add_share_file,share/gowin,techlibs/gowin/brams.txt))
+$(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams_map.v))
+$(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams.txt))
+++ /dev/null
-bram $__GW1NR_SDP
- init 1
- abits 9 @a9d36
- dbits 32 @a9d36
- abits 10 @a10d18
- dbits 16 @a10d18
- abits 11 @a11d9
- dbits 8 @a11d9
- abits 12 @a12d4
- dbits 4 @a12d4
- abits 13 @a13d2
- dbits 2 @a13d2
- abits 14 @a14d1
- dbits 1 @a14d1
- groups 2
- ports 1 1
- wrmode 1 0
- enable 4 1 @a9d36
- enable 2 1 @a10d18
- enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
- transp 0 0
- clocks 2 3
- clkpol 2 3
-endbram
-
-match $__GW1NR_SDP
- min bits 2048
- min efficiency 5
- shuffle_enable A
- make_transp
-endmatch
--- /dev/null
+bram $__GW1NR_SDP
+ init 1
+ abits 9 @a9d36
+ dbits 32 @a9d36
+ abits 10 @a10d18
+ dbits 16 @a10d18
+ abits 11 @a11d9
+ dbits 8 @a11d9
+ abits 12 @a12d4
+ dbits 4 @a12d4
+ abits 13 @a13d2
+ dbits 2 @a13d2
+ abits 14 @a14d1
+ dbits 1 @a14d1
+ groups 2
+ ports 1 1
+ wrmode 1 0
+ enable 4 1 @a9d36
+ enable 2 1 @a10d18
+ enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
+ transp 0 0
+ clocks 2 3
+ clkpol 2 3
+endbram
+
+match $__GW1NR_SDP
+ min bits 2048
+ min efficiency 5
+ shuffle_enable A
+ make_transp
+endmatch
+++ /dev/null
-bram $__GW1NR_RAM16S4
- init 1
- abits 4
- dbits 4
- groups 2
- ports 1 1
- wrmode 0 1
- enable 0 1
- transp 0 1
- clocks 0 1
- clkpol 0 1
-endbram
-
-match $__GW1NR_RAM16S4
- make_outreg
- min wports 1
-endmatch
+++ /dev/null
-module \$__GW1NR_RAM16S4 (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
- parameter CFG_ABITS = 4;
- parameter CFG_DBITS = 4;
-
- parameter [63:0] INIT = 64'bx;
- input CLK1;
-
- input [CFG_ABITS-1:0] A1ADDR;
- output [CFG_DBITS-1:0] A1DATA;
- input A1EN;
-
- input [CFG_ABITS-1:0] B1ADDR;
- input [CFG_DBITS-1:0] B1DATA;
- input B1EN;
-
- `include "brams_init3.vh"
-
- RAM16S4
- #(.INIT_0(INIT_0),
- .INIT_1(INIT_1),
- .INIT_2(INIT_2),
- .INIT_3(INIT_3))
- _TECHMAP_REPLACE_
- (.AD(B1ADDR),
- .DI(B1DATA),
- .DO(A1DATA),
- .CLK(CLK1),
- .WRE(B1EN));
-
-
-endmodule
--- /dev/null
+bram $__GW1NR_RAM16S4
+ init 1
+ abits 4
+ dbits 4
+ groups 2
+ ports 1 1
+ wrmode 0 1
+ enable 0 1
+ transp 0 1
+ clocks 0 1
+ clkpol 0 1
+endbram
+
+match $__GW1NR_RAM16S4
+ make_outreg
+ min wports 1
+endmatch
--- /dev/null
+module \$__GW1NR_RAM16S4 (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
+ parameter CFG_ABITS = 4;
+ parameter CFG_DBITS = 4;
+
+ parameter [63:0] INIT = 64'bx;
+ input CLK1;
+
+ input [CFG_ABITS-1:0] A1ADDR;
+ output [CFG_DBITS-1:0] A1DATA;
+ input A1EN;
+
+ input [CFG_ABITS-1:0] B1ADDR;
+ input [CFG_DBITS-1:0] B1DATA;
+ input B1EN;
+
+ `include "brams_init3.vh"
+
+ RAM16S4
+ #(.INIT_0(INIT_0),
+ .INIT_1(INIT_1),
+ .INIT_2(INIT_2),
+ .INIT_3(INIT_3))
+ _TECHMAP_REPLACE_
+ (.AD(B1ADDR),
+ .DI(B1DATA),
+ .DO(A1DATA),
+ .CLK(CLK1),
+ .WRE(B1EN));
+
+
+endmodule
log(" -nobram\n");
log(" do not use BRAM cells in output netlist\n");
log("\n");
- log(" -nodram\n");
+ log(" -nolutram\n");
log(" do not use distributed RAM cells in output netlist\n");
log("\n");
log(" -noflatten\n");
}
string top_opt, vout_file;
- bool retime, nobram, nodram, flatten, nodffe, nowidelut, abc9, noiopads;
+ bool retime, nobram, nolutram, flatten, nodffe, nowidelut, abc9, noiopads;
void clear_flags() YS_OVERRIDE
{
flatten = true;
nobram = false;
nodffe = false;
- nodram = false;
+ nolutram = false;
nowidelut = false;
abc9 = false;
noiopads = false;
nobram = true;
continue;
}
- if (args[argidx] == "-nodram") {
- nodram = true;
+ if (args[argidx] == "-nolutram" || /*deprecated*/args[argidx] == "-nodram") {
+ nolutram = true;
continue;
}
if (args[argidx] == "-nodffe") {
run("synth -run coarse");
}
- if (!nobram && check_label("bram", "(skip if -nobram)"))
+ if (!nobram && check_label("map_bram", "(skip if -nobram)"))
{
- run("memory_bram -rules +/gowin/bram.txt");
+ run("memory_bram -rules +/gowin/brams.txt");
run("techmap -map +/gowin/brams_map.v -map +/gowin/cells_sim.v");
}
- if (!nodram && check_label("dram", "(skip if -nodram)"))
+ if (!nolutram && check_label("map_lutram", "(skip if -nolutram)"))
{
- run("memory_bram -rules +/gowin/dram.txt");
- run("techmap -map +/gowin/drams_map.v");
+ run("memory_bram -rules +/gowin/lutrams.txt");
+ run("techmap -map +/gowin/lutrams_map.v");
run("determine_init");
}
- if (check_label("fine"))
+ if (check_label("map_ffram"))
{
run("opt -fast -mux_undef -undriven -fine");
run("memory_map");
run("opt -undriven -fine");
+ }
+
+ if (check_label("map_gates"))
+ {
run("techmap -map +/techmap.v -map +/gowin/arith_map.v");
run("techmap -map +/techmap.v");
if (retime || help_mode)
run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O "
"-toutpad TBUF OEN:I:O -tinoutpad IOBUF OEN:O:I:IO", "(unless -noiopads)");
run("clean");
-
}
if (check_label("check"))
}
if (!nobram && check_label("map_bram", "(skip if -nobram)")) {
- if (family_opt == "cycloneiv" ||
- family_opt == "cycloneive" ||
- family_opt == "max10" ||
- help_mode) {
+ if (family_opt == "cycloneiv" ||
+ family_opt == "cycloneive" ||
+ family_opt == "max10" ||
+ help_mode) {
run("memory_bram -rules +/intel/common/brams_m9k.txt", "(if applicable for family)");
run("techmap -map +/intel/common/brams_map_m9k.v", "(if applicable for family)");
} else {
if (check_label("map_cells")) {
if (iopads || help_mode)
run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(if -iopads)");
- run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt.c_str()));
+ run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt.c_str()));
run("dffinit -highlow -ff dffeas q power_up");
run("clean -purge");
}
projects / yosys.git / commitdiff