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diff --git a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
index 06bb1aae6c1185eb3a90e1f655f06292f0b5e95e..f470b2868fe32ff933972d00c8cfe558a998c26d 100644 (file)
--- a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
+++ b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
@@ -1,6 +1,6 @@
 # Comparative analysis of Andes Packed ISA proposal vs RVP Harmonised (with RV Vector spec)
 
-## Proposed vector instruction encoding
+## Proposed Harmonised RVP vector op instruction encoding
 
 Register x 2 -> register operations: