remove last uses of soc

diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py
index 2016876f5da887fd47e6e22d34b5f5e045e89708..839709f7823623be236c50f504532d58407f291e 100644 (file)
--- a/src/openpower/test/runner.py
+++ b/src/openpower/test/runner.py
@@ -15,6 +15,7 @@ related bugs:
  * https://bugs.libre-soc.org/show_bug.cgi?id=686#c51
 """
 
+from unittest.mock import Mock
 from nmigen import Module, ClockSignal
 from copy import copy, deepcopy
 from pprint import pprint
@@ -30,7 +31,6 @@ from openpower.endian import bigendian
 
 from openpower.decoder.power_decoder2 import PowerDecode2
 
-from soc.config.test.test_loadstore import TestMemPspec
 from nmutil.util import wrap
 from openpower.test.wb_get import wb_get
 import openpower.test.wb_get as wbget
@@ -144,24 +144,24 @@ class TestRunnerBase(FHDLTestCase):
             ldst_ifacetype = 'test_bare_wb'
             imem_ifacetype = 'test_bare_wb'
 
-        pspec = TestMemPspec(ldst_ifacetype=ldst_ifacetype,
-                             imem_ifacetype=imem_ifacetype,
-                             addr_wid=64,
-                             mask_wid=8,
-                             XLEN=64,
-                             imem_reg_wid=64,
-                             # wb_data_width=32,
-                             use_pll=False,
-                             nocore=False,
-                             xics=False,
-                             gpio=False,
-                             regreduce=not self.allow_overlap,
-                             core_domain="sync",  # no alternative domain
-                             svp64=self.svp64,
-                             allow_overlap=self.allow_overlap,
-                             inorder=self.inorder,
-                             mmu=self.microwatt_mmu,
-                             reg_wid=64)
+        pspec = Mock(ldst_ifacetype=ldst_ifacetype,
+                     imem_ifacetype=imem_ifacetype,
+                     addr_wid=64,
+                     mask_wid=8,
+                     XLEN=64,
+                     imem_reg_wid=64,
+                     # wb_data_width=32,
+                     use_pll=False,
+                     nocore=False,
+                     xics=False,
+                     gpio=False,
+                     regreduce=not self.allow_overlap,
+                     core_domain="sync",  # no alternative domain
+                     svp64=self.svp64,
+                     allow_overlap=self.allow_overlap,
+                     inorder=self.inorder,
+                     mmu=self.microwatt_mmu,
+                     reg_wid=64)
 
         ###### SETUP PHASE #######
         # Determine the simulations needed and add to state_list

diff --git a/src/openpower/test/test_state_class.py b/src/openpower/test/test_state_class.py
index 918958cfe4c43af4c0b22d08f22933b273805885..b84a4aad3aeb25c8a12c201881a768711c822699 100644 (file)
--- a/src/openpower/test/test_state_class.py
+++ b/src/openpower/test/test_state_class.py
@@ -12,7 +12,6 @@ related bugs:
 import unittest
 import random
 from openpower.test.state import SimState, state_factory
-from soc.simple.test.teststate import HDLState
 
 
 class TestStates(unittest.TestCase):