no svstate instruction

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index c1610c4e682b05b98fba3bf8ea11ada1bc77bef4..3b94fe2c91c891ab26d80b686cc173f1814819d9 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1692,8 +1692,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
 
         # see if srcstep/dststep need skipping over masked-out predicate bits
         self.reset_remaps()
-        if (self.is_svp64_mode or ins_name in ['svstep',
-          'svremap', 'svstate']):
+        if (self.is_svp64_mode or ins_name in ['svstep', 'svremap']):
             yield from self.svstate_pre_inc()
         if self.is_svp64_mode:
             pre = yield from self.update_new_svstate_steps()