soc/sdram: Vivado 2015.1 still does not fix issue with L2 cache, update comment...

diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py
index 1d96d280b6eef096ec60bcef089df1849e64336e..44ad29bc8983ecf8572091e0bd83fe1e8180dcdc 100644 (file)
--- a/misoclib/soc/sdram.py
+++ b/misoclib/soc/sdram.py
@@ -59,8 +59,8 @@ class SDRAMSoC(SoC):
 
             l2_size = self.sdram_controller_settings.l2_size
             if l2_size:
-                # XXX Vivado 2014.X workaround, Vivado is not able to map correctly our L2 cache.
-                # Issue is reported to Xilinx and should be fixed in next releases (2015.1?).
+                # XXX Vivado ->2015.1 workaround, Vivado is not able to map correctly our L2 cache.
+                # Issue is reported to Xilinx and should be fixed in next releases (2015.2?).
                 # Remove this workaround when fixed by Xilinx.
                 from mibuild.xilinx.vivado import XilinxVivadoToolchain
                 if isinstance(self.platform.toolchain, XilinxVivadoToolchain):