targets/simple: make it generic (no default_platform, use platform's default_clk_name...

diff --git a/make.py b/make.py
index 108c9fa6a0ec998c3f63552fb2a3d0d97aee0da0..bf11452e377cd6013819524fec6b6db7e383b4fa 100755 (executable)
--- a/make.py
+++ b/make.py
@@ -69,7 +69,10 @@ if __name__ == "__main__":
                top_class = target_module.default_subtarget
 
        if args.platform is None:
-               platform_name = top_class.default_platform
+               if hasattr(top_class, "default_platform"):
+                       platform_name = top_class.default_platform
+               else:
+                       raise ValueError("Target has no default platform, specify a platform with -p your_platform")
        else:
                platform_name = args.platform
        platform_module = misoc_import("mibuild.platforms", external_platform, platform_name)

diff --git a/targets/simple.py b/targets/simple.py
index f88f866999539cf5de603259a80998b75fec9c30..f4b0ffdb52dafb3b1bcbd6d4cb6741c844b98870 100644 (file)
--- a/targets/simple.py
+++ b/targets/simple.py
@@ -18,17 +18,13 @@ class _CRG(Module):
                ]
 
 class SimpleSoC(GenSoC, IntegratedBIOS):
-       default_platform = "de0nano"    # /!\ Adapt this!
-       clk_name = "clk50"                              # /!\ Adapt this!
-       clk_freq = 50*1000000                   # /!\ Adapt this!
-
        def __init__(self, platform):
                GenSoC.__init__(self, platform,
-                       clk_freq=self.clk_freq,
+                       clk_freq=int((1/(platform.default_clk_period))*1000000000),
                        cpu_reset_address=0)
                IntegratedBIOS.__init__(self)
 
-               self.submodules.crg = _CRG(platform.request(self.clk_name))
+               self.submodules.crg = _CRG(platform.request(platform.default_clk_name))
 
                # use on-board SRAM as SDRAM
                sys_ram_size = 16*1024